000			05071nam a22004573i 4500
001			EBC5122088
003			MiAaPQ
005			20240729131547.0
006			m o d |
007			cr cnu||||||||
008			240724s2017 xx o ||||0 eng d
020			_a9781119467144 _q(electronic bk.)
020			_z9781786300942
035			_a(MiAaPQ)EBC5122088
035			_a(Au-PeEL)EBL5122088
035			_a(CaPaEBR)ebr11463977
035			_a(OCoLC)1008962948
040			_aMiAaPQ _beng _erda _epn _cMiAaPQ _dMiAaPQ
050		4	_aTA1637.C436 2017
082	0		_a621.367
100	1		_aLi, Chao.
245	1	0	_aArchitecture-Aware Optimization Strategies in Real-Time Image Processing.
250			_a1st ed.
264		1	_aNewark : _bJohn Wiley & Sons, Incorporated, _c2017.
264		4	_c©2017.
300			_a1 online resource (185 pages)
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
505	0		_aCover -- Half-Title Page -- Title Page -- Copyright Page -- Contents -- Preface -- 1. Introduction of Real-time Image Processing -- 1.1. General image processing presentation -- 1.2. Real-time image processing -- 2. Hardware Architectures for Real-time Processing -- 2.1. History of image processing hardware platforms -- 2.2. General-purpose processors -- 2.3. Digital signal processors -- 2.4. Graphics processing units -- 2.5. Field programmable gate arrays -- 2.6. SW/HW codesign of real-time image processing -- 2.7. Image processing development environment description -- 2.8. Comparison and discussion -- 3. Rapid Prototyping of Parallel Reconfigurable Instruction Set Processor for Efficient Real-Time Image Processing -- 3.1. Context and problematic -- 3.2. Related works -- 3.3. Design exploration framework -- 3.4. Case study: RISP conception and synthesis for spatial transforms -- 3.4.1. Digital DCT algorithm implementations -- 3.4.2. Rapid prototyping of DCT RISP conception -- 3.4.3. RISP simulation and synthesis for 2D-DCT -- 3.5. Hardware implementation of spatial transforms on an FPGA-based platform -- 3.6. Discussion and conclusion -- 4. Exploration of High-level Synthesis Technique -- 4.1. Introduction of HLS technique -- 4.2. Vivado_HLS process presentation -- 4.2.1. Control and datapath extraction -- 4.2.2. Scheduling and binding -- 4.3. Case of HLS application: FPGA implementation of an improved skin lesion assessment method -- 4.3.1. KMGA method description -- 4.3.2. KMGA method optimization -- 4.3.3. HCR-KMGA implementation onto FPGA using HLS technique -- 4.3.4. Implementation evaluation experiments -- 4.4. Discussion -- 5. CDMS4HLS: A Novel Source-To-Source Compilation Strategy for HLS-Based FPGA Design -- 5.1. S2S compiler-based HLS design framework -- 5.2. CDMS4HLS compilation process description -- 5.2.1. Function inline.
505	8		_a5.2.2. Loop manipulation -- 5.2.3. Symbolic expression manipulation -- 5.2.4. Loop unwinding -- 5.2.5. Memory manipulation -- 5.3. CDMS4HLS compilation process evaluation -- 5.3.1. Performances improvement evaluation -- 5.3.2. Comparison experiment -- 5.4. Discussion -- 6. Embedded Implementation of VHR Satellite Image Segmentation -- 6.1. LSM description -- 6.1.1. Background -- 6.1.2. Level set equation -- 6.1.3. LBM solver -- 6.2. Implementation and optimization presentation -- 6.2.1. Design flow description -- 6.2.2. Algorithm analysis -- 6.2.3. Function inline -- 6.2.4. Loop manipulation -- 6.2.5. Symbol expression manipulation -- 6.2.6. Loop unwinding -- 6.3. Experiment evaluation -- 6.3.1. Parameter configuration -- 6.3.2. Function verification -- 6.3.3. Optimization evaluation -- 6.3.4. Performance comparison -- 6.4. Discussion and conclusion -- 7. Real-time Image Processing with Very High-level Synthesis -- 7.1. VHLS motivation -- 7.2. Image processing from Matlab to FPGA-RTL -- 7.3. VHLS process presentation -- 7.3.1. Dynamic variable -- 7.3.2. Operation polymorphism problem -- 7.3.3. Built-in function problem -- 7.4. VHLS implementation issues -- 7.4.1. Work flow -- 7.4.2. Intermediate code versus RTL -- 7.4.3. SSC versus HLS -- 7.4.4. Verification and evaluation -- 7.5. Future work for real-time image processing with VHLS -- Bibliography -- Index -- Other titles from iSTE in Digital Signal and Image Processing -- EULA.
588			_aDescription based on publisher supplied metadata and other sources.
590			_aElectronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2024. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries.
650		0	_aImage processing--Digital techniques.
655		4	_aElectronic books.
700	1		_aBalla-Arabe, Souleymane.
700	1		_aYang, Fan.
776	0	8	_iPrint version: _aLi, Chao _tArchitecture-Aware Optimization Strategies in Real-Time Image Processing _dNewark : John Wiley & Sons, Incorporated,c2017 _z9781786300942
797	2		_aProQuest (Firm)
856	4	0	_uhttps://ebookcentral.proquest.com/lib/orpp/detail.action?docID=5122088 _zClick to View
999			_c132171 _d132171