Real-Time Multi-Chip Neural Network for Cognitive Systems.

Cover -- Half Title -- Series -- Title -- Copyright -- Dedication -- Table of Contents -- Preface -- List of Contributors -- List of Figures -- List of Tables -- List of Abbreviations -- 1 Introduction -- 1.1 A Real-Time Reconfigurable Multi-Chip Architecture for Large-Scale Biophysically Accurate Neuron Simulation -- 1.2 The Inferior Olivary Nucleus Cell -- 1.2.1 Abstract Model Description -- 1.2.2 The ION Cell Design Configuration -- 1.2.3 The ION Cell Cluster Controller -- 1.3 Multi-Chip Dataflow Architecture -- 1.4 Organization of the Book -- References -- 2 Multi-Chip Dataflow Architecture for Massive Scale Biophysically Accurate Neuron Simulation -- 2.1 Introduction -- 2.2 System Design Configuration -- 2.2.1 Requirements -- 2.2.2 Zero Communication Time: The Optimal Approach -- 2.2.3 Localising Communication: How to Speed Up the Common Case -- 2.2.4 Network-on-Chips -- 2.2.5 Localise Communication between Clusters -- 2.2.6 Synchronisation between the Clusters -- 2.2.7 Adjustments to the Network to Scale over Multiple FPGAs -- 2.2.8 Interfacing the Outside World: Inputs and Outputs -- 2.2.9 Adding Flexibility: Run-Time Configuration -- 2.2.10 Parameters of the System -- 2.2.11 Connectivity and Structure Generation -- 2.3 System Implementation -- 2.3.1 Exploiting Locality: Clusters -- 2.3.2 Connecting Clusters: Routers -- 2.3.3 Tracking Time: Iteration Controller -- 2.3.4 Inputs and Outputs -- 2.3.5 The Control Bus for Run-Time Configuration -- 2.3.6 Automatic Structure Generation and Connectivity Generation -- 2.4 Experimental Results -- 2.5 Conclusions -- References -- 3 A Real-Time Hybrid Neuron Network for Highly Parallel Cognitive Systems -- 3.1 Introduction -- 3.2 The Calculation Architecture -- 3.2.1 The Physical Cell Overview -- 3.2.2 Initialising the Physical Cells -- 3.2.3 Axon Hillock + Soma Hardware.

3.2.3.1 Exponent operand schedule -- 3.2.3.2 Axon hillock and soma compartment controller -- 3.2.4 Dendrite Hardware -- 3.2.4.1 Dendrite network operation -- 3.2.4.2 Dendrite combine operation -- 3.2.4.3 Dendrite compartmental latency -- 3.2.5 Calculation Architecture Latency -- 3.2.6 Exponent Architecture -- 3.3 The Calculation Architecture -- 3.3.1 Communication Architecture Overview -- 3.3.2 Cluster Controller -- 3.3.3 Routing Network -- 3.3.3.1 Routing method -- 3.3.3.2 Design specification -- 3.3.4 Interface Bridge -- 3.4 Experimental Results -- 3.4.1 Evaluation Method -- 3.4.1.1 Building a test set -- 3.4.1.2 Design simulation -- 3.4.1.3 SystemC synthesis -- 3.4.1.4 Post-synthesis simulation -- 3.4.1.5 VHDL implementation -- 3.4.2 Evaluation Results -- 3.4.2.1 Accuracy results -- 3.4.2.2 Latency results -- 3.4.2.3 Resource usage -- 3.4.3 Model Configuration -- 3.5 Conclusions -- References -- 4 Digital Neuron Cells for Highly Parallel Cognitive Systems -- 4.1 Introduction -- 4.2 System Design Configuration -- 4.2.1 Requirements -- 4.2.2 Input and Output -- 4.2.3 Parameters -- 4.2.4 Scalability of Network -- 4.2.5 Neuron Models Implementations -- 4.2.6 Synthesis -- 4.3 System Design Implementation -- 4.3.1 Interface -- 4.3.1.1 Inputs and outputs -- 4.3.1.2 Locality of data -- 4.3.1.2.1 Localization of inputs -- 4.3.1.2.2 Localization of outputs -- 4.3.2 Implementation of the Neuron Models -- 4.3.2.1 The extended Hodgkin-Huxley model -- 4.3.2.1.1 Neuron cell -- 4.3.2.1.2 Physical cell -- 4.3.2.1.3 Cluster -- 4.3.2.2 Integrate-and-fire model -- 4.3.2.3 Izhikevich model -- 4.3.2.3.1 Axonal conduction delay -- 4.3.2.3.2 STDP -- 4.3.2.3.3 Spike generation -- 4.3.3 High-level Synthesis -- 4.3.3.1 Optimization with directives -- 4.3.3.2 Adjustments of system for HLS -- 4.3.3.2.1 Hodgkin-Huxley model -- 4.3.3.2.2 Integrate-and-fire model.

4.3.3.2.3 Izhikevich model -- 4.4 Performance Evaluation -- 4.4.1 Model Configuration -- 4.4.2 Experimental Results -- 4.5 Conclusions -- References -- 5 Energy-Efficient Multipath Ring Network for Heterogeneous Clustered Neuronal Arrays -- 5.1 Introduction -- 5.2 State-of-the-Art and Background Concepts -- 5.2.1 Neuron Models -- 5.2.2 Simulation Platforms -- 5.2.3 Communication Network Considerations -- 5.3 Neural Network Communication Schemes and System Structure -- 5.3.1 Physical System Structure -- 5.3.2 Extraction, Insertion, and Configuration Layer -- 5.3.3 Topological Layer -- 5.3.3.1 Multipath ring routing scheme -- 5.3.3.2 Traffic model -- 5.4 Energy-Delay Product -- 5.4.1 Mathematical Derivation -- 5.4.2 Energy-Delay Product Estimation -- 5.5 Conclusions -- References -- 6 A Hierarchical Dataflow Architecture for Large-Scale Multi-FPGA Biophysically Accurate Neuron Simulation -- 6.1 Introduction -- 6.2 The System Overview -- 6.2.1 Mesh Topology -- 6.2.2 The Routers -- 6.2.3 The Clusters -- 6.2.4 Hodgkin-Huxley Cells -- 6.3 The Communication Architecture -- 6.4 Experimental Results -- 6.5 Conclusions -- References -- 7 Single-Lead Neuromorphic ECG Classification System -- 7.1 Introduction -- 7.1.1 ECG Signals and Arrhythmia -- 7.1.2 Feature Detection -- 7.1.2.1 Methods and algorithms -- 7.1.2.1.1 QRS detection -- 7.1.2.1.2 P and T wave detection -- 7.1.3 Feature Selection -- 7.1.3.1 Feature selection choices -- 7.1.3.2 Methods and algorithms -- 7.1.4 Classification Methods -- 7.2 Feature Extraction Implementation -- 7.2.1 Feature Detection -- 7.2.1.1 QRS detection -- 7.2.1.2 P and T wave detection -- 7.2.2 Feature Selection -- 7.2.2.1 Feature set -- 7.2.2.2 Correlation matrix -- 7.3 Network Configuration and Results -- 7.3.1 Approach -- 7.3.2 Silhouette Coefficients -- 7.3.3 Clustering Methods for the Output -- 7.3.4 Results.

7.4 Conclusion -- References -- 8 Multi-Compartment Synaptic Circuit in Neuromorphic Structures -- 8.1 Introduction -- 8.1.1 Synapse -- 8.1.1.1 Synaptic plasticity -- 8.1.1.2 Synaptic receptors -- 8.1.1.2.1 AMPA receptor -- 8.1.1.2.2 NMDA receptor -- 8.1.1.2.3 GABA receptor -- 8.2 Model Extraction -- 8.2.1 Model of the Synapse -- 8.2.2 Learning Rules -- 8.2.2.1 Pair-based STDP -- 8.2.2.1.1 Triplet-based STDP -- 8.3 Component Implementations -- 8.3.1 Learning Rule 1: Classic STDP -- 8.3.2 Learning Rule 2: Advanced STDP -- 8.3.3 Learning Rule 3: Triplet-Based STDP -- 8.3.4 Synaptic Receptors -- 8.3.4.1 AMPA receptor -- 8.3.4.2 NMDA receptor -- 8.3.4.3 GABA receptors -- 8.4 Component Characterizations -- 8.4.1 Learning Rule 1: Classic STDP -- 8.4.2 Learning Rule 2: Advanced STDP -- 8.4.3 Learning Rule 3: Triplet-based STDP -- 8.4.4 Synaptic Receptors -- 8.4.4.1 Environment settings -- 8.4.4.2 Results -- 8.5 Neural Network with Multi-Receptor Synapses -- 8.5.1 Synchrony Detection Tool: Cross-Correlograms -- 8.5.2 Environment Settings -- 8.5.3 Input Patterns -- 8.5.4 Synchrony Detection -- 8.6 Conclusions -- References -- 9 Conclusion and Future Work -- 9.1 Summary of the Results -- 9.2 Recommendations and Future Work -- Index -- About the Editors.

Real-Time Multi-Chip Neural Network for Cognitive Systems presents novel real-time, reconfigurable, multi-chip SNN system architecture based on localized communication, which effectively reduces the communication cost to a linear growth.

Description based on publisher supplied metadata and other sources.

Electronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2024. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries.