Layout Techniques for Integrated Circuit Designers.

Intro -- Layout Techniques for Integrated Circuit Designers -- Contents -- Preface -- Chapter 1 Introduction -- Part I: Manufacturing and Physical Layout Techniques -- Chapter 2 Preliminaries -- 2.1 Silicon Manufacturing Basics -- 2.1.1 Basic Overview -- 2.1.2 Epitaxy -- 2.1.3 Oxidation -- 2.1.4 Photolithography -- 2.1.5 Etching -- 2.1.6 Doping -- 2.1.7 Deposition -- 2.1.8 Planarization -- 2.1.9 Wafer Stack-Up -- 2.1.10 Thinning -- 2.1.11 Singulation (Dicing/Cutting) -- 2.1.12 Bonding -- 2.1.13 Bumping -- 2.1.14 Packaging -- 2.1.15 Wafer-Level Probe Test -- 2.1.16 Final Test -- 2.2 Semiconductor Yield -- 2.2.1 Functional Yield -- 2.2.2 Parametric Yield -- 2.3 Layout Database Formats -- 2.3.1 Calma and GDSII -- 2.3.2 OASIS and Open Access -- 2.4 Schematic Netlist Formats -- 2.4.1 SPICE Format -- 2.4.2 CDL Format -- 2.4.3 Spectre Format -- 2.5 Simulation Output Formats -- 2.6 Formats Used in the Book -- 2.7 Summary -- Exercises -- References -- Chapter 3 Device Formation in Layout -- 3.1 Process Stack-Up -- 3.2 Fundamental Devices -- 3.2.1 Silicide Formation -- 3.2.2 Resistors -- 3.2.3 Maxwell's Equations -- 3.2.4 Capacitors -- 3.2.5 Inductors -- 3.2.6 Transmission Lines -- 3.2.7 MOSFET Devices -- 3.2.8 Bipolar Transistor Devices -- 3.2.9 Summary of Device Manufacturing -- 3.3 Device Matching -- 3.3.1 Process-Related Causes of Mismatch -- 3.3.2 Layout Strategies to Minimize Mismatch -- 3.3.3 Design Strategies to Reduce the Effect of Mismatch -- 3.4 Manufacturing Challenges: Design Rules -- 3.4.1 Design Rule Derivations -- 3.4.2 Width Rules -- 3.4.3 Spacing Rules -- 3.4.4 Enclosure/Overlap Rules -- 3.4.5 Area Rules -- 3.4.6 Antenna Rules -- 3.4.7 Density Rules -- 3.5 Future Directions -- 3.6 Summary -- Exercises -- References -- Chapter 4 Layout with Ultrasmall Geometry CMOS Technologies -- 4.1 Small Geometry Effects -- 4.1.1 Thin Metal Effects.

4.1.2 Strain Effects -- 4.1.3 Well Proximity Effect -- 4.1.4 Substrate Contact Distance Requirements -- 4.1.5 EM and IR Drop -- 4.2 Small Geometry CMOS Flow -- 4.2.1 Strategies to Manage High-Resistance Interconnect -- 4.2.2 Strategies to Manage Parasitic Capacitance -- 4.2.3 Strategies to Manage Parasitic Inductance -- 4.2.4 Overall Parasitic Strategies -- 4.3 Summary -- Exercises -- References -- Chapter 5 Layout with Bipolar Technologies SiGe -- 5.1 Introduction -- 5.2 Process Flow -- 5.2.1 Physics of SiGe Bipolar Transistors -- 5.2.2 Collector Formation -- 5.2.3 Base Formation -- 5.2.4 Emitter Formation -- 5.2.5 Parasitics of Bipolar Transistors -- 5.2.6 PNP Transistors -- 5.2.7 Future Direction of SiGe transistors -- 5.3 Layout Flow -- 5.3.1 SIGe Technology Metallization -- 5.3.2 Transistor Layout Topologies -- 5.4 Other Technologies -- 5.4.1 InP HBT -- 5.4.2 GaAs HBT -- 5.4.3 Comparison of Different HBT Technologies -- 5.5 Summary -- References -- Chapter 6 Aspects of High-Speed Layout 10-100+ GHz -- 6.1 Single-Ended Transmission Lines On-Chip -- 6.1.1 Layout Applications -- 6.2 Interface to Package and Circuit Board -- 6.2.1 Impedance-Matching Review -- 6.2.2 S-Paramters: What Does Matching Mean? -- 6.2.3 Impedance Matching: Circuit-Level Analysis -- 6.2.4 T-Coil Theory -- 6.2.5 Summary -- 6.3 Coupled Transmission Lines On-Chip -- 6.3.1 Fundamental Properties -- 6.3.2 Power Waves -- 6.3.3 Eigenmodes -- 6.3.4 Solution with Eigenmodes -- 6.3.5 Examples of Coupled Transmission Lines -- 6.4 Inductors and Capacitors at High Frequencies -- 6.4.1 Skin Effect -- 6.5 Layout Strategies -- 6.5.1 High-Speed Analog Blocks -- 6.5.2 Analog and Digital Block Coexistence -- 6.6 Summary -- Exercises -- References -- Part II: Layout Verification Techniques -- Chapter 7 Extraction Techniques -- 7.1 Introduction -- 7.2 Basic Geometric Algorithms on Polygons.

7.2.1 Definition of Polygons for Use in Layout Databases -- 7.2.2 Geometric Operations on Polygons -- 7.2.3 Geometric Operations in the Literature -- 7.3 Device Recognition Algorithms -- 7.3.1 Basic Technology -- 7.3.2 Supporting Software Architecture -- 7.3.3 Device Recognition Fundamentals -- 7.4 An Efficient Search Algorithm: k-d Tree -- 7.5 Connectivity Algorithms -- 7.5.1 Flat Layout Extraction -- 7.5.2 Hierarchical Layout Extraction -- 7.6 Parasitic Device Extraction -- 7.7 Summary -- Exercises -- References -- Chapter 8 Netlist Comparators -- 8.1 Historical Development -- 8.2 Mathematical Basis -- 8.2.1 Graph Theory Definitions -- 8.2.2 Graph Isomorphism Problem -- 8.3 A Few Simple Examples on Comparing Netlists -- 8.3.1 Some Specific Situations -- 8.4 A Python Implementation -- 8.4.1 Node Connectivity Algorithm -- 8.4.2 Build a Match Matrix -- 8.4.3 Single Matching Algorithm -- 8.4.4 Matrix AND Operation -- 8.4.5 Isomorphism Verification Algorithm -- 8.4.6 Symmetry Match -- 8.4.7 Various Administrative Routines -- 8.4.8 Netlist Comparator -- 8.4.9 Various Improvements -- 8.5 A Larger Example with Unmatched Netlists -- 8.5.1 LVS Debug Report -- 8.5.2 A Mismatched Pair of Netlists -- 8.5.3 Summary -- 8.6 Other Algorithms -- 8.7 A Real-World LVS Flow for Integrated Circuits -- 8.8 Summary -- Exercises -- References -- Chapter 9 Design Rule Checkers -- 9.1 Implementations of Design Rules -- 9.1.1 Basic Data Structure -- 9.1.2 Implementing Basic Width Rules -- 9.1.3 Implementing Basic Spacing Rules -- 9.1.4 Interdependent Spacing and Width Rules -- 9.1.5 Overlap and Enclosure Rules -- 9.1.6 Notch Rules -- 9.1.7 Antenna Rules -- 9.1.8 Area Rules -- 9.1.9 Density Rules -- 9.1.10 Colorization and Related Complexities -- 9.2 Summary -- Exercies -- References -- Acronyms and Abbreviations -- Index.

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Electronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2024. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries.