DataFlow Supercomputing Essentials : Research, Development and Education.

Intro -- Preface -- Dataflow Taxonomy -- Maxeler -- Research Issues -- Application Issues -- Conclusion -- Contents -- Part I Research -- 1 Maxeler AppGallery Revisited -- 1.1 Introduction -- 1.2 Maxeler AppGallery -- 1.2.1 Data Analytics Category -- 1.2.1.1 Sequential Monte Carlo -- 1.2.1.2 Real-Time VaR Monitoring -- 1.2.1.3 Boosted Decision Tree Classifier -- 1.2.1.4 Heston Option Pricer -- 1.2.2 Engineering Category -- 1.2.2.1 Motion Estimation -- 1.2.2.2 Real-time 4k Ultra HD Video -- 1.2.2.3 Gzip Compression -- 1.2.3 Low Latency Transaction Processing Category -- 1.2.3.1 HFTDemo -- 1.2.4 Networking Category -- 1.2.4.1 High-Speed Packet Capture -- 1.2.4.2 Packet Pusher -- 1.2.4.3 Low-Latency HTTP Web Server -- 1.2.5 Science Category -- 1.2.5.1 Reverse Time Migration -- 1.2.5.2 Network Sorting -- 1.2.5.3 Localization Microscopy -- 1.2.6 Security Category -- 1.2.6.1 Fully Homomorphic Encryption -- References -- 2 Discrepancy Reduction Between the Topology of Dataflow Graph and the Topology of FPGA Structure -- 2.1 Introduction -- 2.2 Dataflow Graph -- 2.3 Getting to Accelerated Application: Maxeler Way -- 2.4 Simulation Debugging -- 2.4.1 Simulation Watches -- 2.4.2 Simulation printf -- 2.5 Hardware Debugging -- 2.5.1 DFE printf -- 2.6 Advanced Debugging -- 2.6.1 Introduction -- 2.6.2 Kernel Halted on Input -- 2.6.3 Kernel Halted on Output -- 2.6.4 Stream Status Blocks -- 2.6.5 Deadlock -- 2.6.5.1 Deadlock Due To: Kernel Has Scheduled an Input Before an Output -- 2.6.5.2 Deadlock Due to: FIFO Ends Up Full -- 2.7 Effects of Inconsistency Between Simulation and Hardware -- 2.7.1 Uninitialized Elements -- 2.7.2 Race Condition -- 2.8 Embedded DFE Optimizations -- 2.8.1 Kernel Optimizations -- 2.8.1.1 Holistic Optimization -- 2.8.1.2 Push-Pop Optimizations -- 2.8.1.3 Placement Constraints -- 2.8.1.4 Input Registering.

2.8.1.5 Per-Stream Optimizations -- 2.8.2 Manager Optimizations -- 2.8.2.1 LMem Clock Frequency -- 2.8.2.2 Stream Clock Frequency -- 2.9 Global DFE Optimization Practices: Getting Maximum Performance -- 2.9.1 Introduction -- 2.9.2 Dataflow Computing Strategy -- 2.9.3 Fitting Procedure -- 2.9.3.1 Techniques to Fit Designs Onto DFE -- 2.9.4 How to Make it Fit? -- 2.9.4.1 Stage 1: DFE Logic Utilization &gt -- 100%: Macro-optimization -- 2.9.4.2 Stage 2: DFE Logic Utilization &gt -- 80% and &lt -- 100%, Micro-optimizations -- 2.9.4.3 Stage 3: DFE Logic Utilization &lt -- 80%, Frequency Optimization -- 2.9.5 Optimizing Memory Bound Applications: Data Size -- 2.9.5.1 Differences in Memory Controllers of Different Cards -- 2.9.5.2 Data-Specific Compression -- 2.9.5.3 Data Encoding -- 2.9.5.4 Reorganization of the Order of Computations -- 2.9.6 Optimizing Compute Performance: Clock Frequency -- 2.10 The More We Know About the Universe, It Is Harder to Believe in Determinism -- 2.10.1 Place and Route Non-deterministic Process -- 2.11 Topology of the Execution Graph -- 2.11.1 Simulated Annealing -- 2.11.2 Cost Tables -- 2.11.3 Constraints -- 2.11.3.1 Implicit -- 2.11.3.2 Frequency -- 2.11.3.3 Configuring Mapping Process -- 2.11.3.4 setBuildEffort(Effort effort) -- 2.11.3.5 setEnablePhysicalSynthesisRegDuplication(Switch switch) -- 2.11.3.6 setMPPRCostTableSearchRange(int min, int max) -- 2.11.3.7 setMPPRParallelism(int numberOfThreads) -- 2.11.3.8 setMPPRRetryNearMissesThreshold(int retryTreshold) -- 2.11.3.9 setOptimizationGoal(OptimizationTechnique technique)) -- 2.12 Topology Inconsistencies -- 2.12.1 Consequences -- 2.13 Compiling Two-Input and Tri-Input Adders -- 2.13.1 Initial Compiling -- 2.13.2 Optimization TriAD Graph Pass -- 2.14 Conclusion -- References -- Part II Development -- 3 Polynomial and Rational Functions -- 3.1 Introduction.

3.1.1 Term of a Real Number -- 3.1.2 Term of a Complex Number -- 3.1.3 The Term of Polynomial -- 3.1.3.1 Definition -- 3.1.4 The Term of Rational Functions -- 3.1.4.1 Definition -- 3.2 Existing Solutions -- 3.3 Essence of the Dataflow Implementation -- 3.4 Details of the Implementation -- 3.4.1 Lexical Analyzer -- 3.4.1.1 Purpose of the Lexical Analyzer -- 3.4.1.2 Tokens -- 3.4.1.3 Patterns -- 3.5 Syntax Analyzer -- 3.5.1 Syntax -- 3.6 Demonstrating the Calculation of a Rational Function's Value -- 3.7 Some Performance Indicators -- 3.8 Conclusions -- References -- 4 Transforming Applications from the Control Flow to the Dataflow Paradigm -- 4.1 Introduction -- 4.1.1 Potentials for Improving Computational Efficiency -- 4.1.2 Potentials for Reducing Power Consumption -- 4.2 Problem Description -- 4.3 Available Dataflow Applications and Technology -- 4.4 Transforming Applications from Control Flow to Dataflow -- 4.5 Analysis of Potentials -- 4.5.1 Huxley Muscle Model -- 4.5.2 Network Sorting -- 4.6 Conclusions -- References -- Part III Education -- 5 Mini Tutorial -- 5.1 Introduction -- 5.2 Dataflow Programming -- 5.2.1 Application Types -- 5.2.2 Educational Value -- 5.2.3 Visual Versus Textual -- 5.3 Installing the Virtual Machine and Starting the Integrated Development Environment -- 5.3.1 Installing the Virtual Machine -- 5.3.2 Integrated Development Environment -- 5.4 First Maxeler Program: ``Hello World'' -- 5.5 Testing the ``Hello World'' Program -- 5.6 Complex Maxeler Program: ``Moving Average'' -- 5.7 Tutorials on YouTube -- References -- Index.

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Electronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2024. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries.