Ultra Low Power Electronics and Adiabatic Solutions.

Cover -- Title Page -- Copyright -- Contents -- Introduction -- 1. Dissipation Sources in Electronic Circuits -- 1.1. Brief description of logic types -- 1.1.1. Boolean logic -- 1.1.2. Combinational and sequential logic -- 1.1.3. NMOS and PMOS transistors -- 1.1.4. Complementary CMOS logic -- 1.1.5. Pass-transistor logic -- 1.1.6. Dynamic logic -- 1.2. Origins of heat dissipation in circuits -- 1.2.1. Joule effect in circuits -- 1.2.2. Calculating dynamic power -- 1.2.3. Calculating static power and its origins -- 2. Thermodynamics and Information Theory -- 2.1. Recalling the basics: entropy and information -- 2.1.1. Statistical definition of entropy -- 2.1.2. Macroscopic energy and entropy -- 2.1.3. Thermostat exchange, Boltzmann's law and the equal division of energy -- 2.1.4. Summary and example of energy production in a conductor carrying a current -- 2.1.5. Information and the associated entropy -- 2.2. Presenting Landauer's principle -- 2.2.1. Presenting Landauer's principle and other examples -- 2.2.2. Experimental validations of Landauer's principle -- 2.3. Adiabaticity and reversibility -- 2.3.1. Adiabatic principle of charging capacitors -- 2.3.2. Adiabaticity and reversibility: a circuit approach -- 3. Transistor Models in CMOS Technology -- 3.1. Reminder on semiconductor properties -- 3.1.1. State densities and semiconductor properties -- 3.1.2. Currents in a semiconductor -- 3.1.3. Contact potentials -- 3.1.4. Metal-oxide semiconductor structure -- 3.1.5. Weak and strong inversion -- 3.2. Long- and short-channel static models -- 3.2.1. Basic principle and brief history of semiconductor technology -- 3.2.2. Transistor architecture and Fermi pseudo-potentials -- 3.2.3. Calculating the current in a long-channel static regime -- 3.2.4. Calculating the current in a short-channel regime -- 3.3. Dynamic transistor models.

3.3.1. Quasi-static regime -- 3.3.2. Dynamic regime -- 3.3.3. "Small signals" transistor model -- 4. Practical and Theoretical Limits of CMOS Technology -- 4.1. Speed-dissipation trade-off and limits of CMOS technology -- 4.1.1. From the transistor to the integrated circuit -- 4.1.2. Trade-off between speed and consumption -- 4.1.3. The trade-off between dynamic consumption and static consumption -- 4.2. Sub-threshold regimes -- 4.2.1. Recall of the weak inversion properties -- 4.2.2. Limits to sub-threshold CMOS technology -- 4.3. Practical and theoretical limits in CMOS technology -- 4.3.1. Economic considerations and evolving methodologies -- 4.3.2. Technological difficulties: dissipation, variability and interconnects -- 4.3.3. Theoretical limits and open questions -- 5. Very Low Consumption at System Level -- 5.1. The evolution of power management technologies -- 5.1.1. Basic techniques for reducing dynamic power -- 5.1.2. Basic techniques for reducing static power -- 5.1.3. Designing in 90, 65 and 45 nm technology -- 5.2. Sub-threshold integrated circuits -- 5.2.1. Sub-threshold circuit features -- 5.2.2. Pipeline and parallelization -- 5.2.3. New SRAM structure -- 5.3. Near-threshold circuits -- 5.3.1. Optimization method -- 5.4. Chip interconnect and networks -- 5.4.1. Dissipation in the interconnect -- 5.4.2. Techniques for reducing dissipation in the interconnect -- 6. Reversible Computing and Quantum Computing -- 6.1. The basis for reversible computing -- 6.1.1. Introduction -- 6.1.2. Group structure of reversible gates -- 6.1.3. Conservative gates, linearity and affinity -- 6.1.4. Exchange gates -- 6.1.5. Control gates -- 6.1.6. Two basic theorems: "no fan-out" and "no cloning" -- 6.2. A few elements for synthesizing a function -- 6.2.1. The problem and constraints on synthesis -- 6.2.2. Synthesizing a reversible function.

6.2.3. Synthesizing an irreversible function -- 6.2.4. The adder example -- 6.2.5. Hardware implementation of reversible gates -- 6.3. Reversible computing and quantum computing -- 6.3.1. Principles of quantum computing -- 6.3.2. Entanglement -- 6.3.3. A few examples of quantum gates -- 6.3.4. The example of Grover's algorithm -- 7. Quasi-adiabatic CMOS Circuits -- 7.1. Adiabatic logic gates in CMOS -- 7.1.1. Implementing the principles of optimal charge and adiabatic pipeline -- 7.1.2. ECRL and PFAL in CMOS -- 7.1.3. Comparison to other gate technologies -- 7.2. Calculation of dissipation in an adiabatic circuit -- 7.2.1. Calculation in the normal regime -- 7.2.2. Calculation in sub-threshold regimes -- 7.3. Energy-recovery supplies and their contribution to dissipation -- 7.3.1. Capacitor-based supply -- 7.3.2. Inductance-based supply -- 7.4. Adiabatic arithmetic architecture -- 7.4.1. Basic principles -- 7.4.2. Adder example -- 7.4.3. The interest in complex gates -- 8. Micro-relay Based Technology -- 8.1. The physics of micro-relays -- 8.1.1. Different computing technologies -- 8.1.2. Different actuation technologies -- 8.1.3. Dynamic modeling of micro-electro-mechanical relays -- 8.1.4. Implementation examples and technological difficulties -- 8.2. Calculation of dissipation in a micro-relay based circuit -- 8.2.1. Optimization of micro-relays through electrostatic actuati -- 8.2.2. Adiabatic regime solutions -- 8.2.3. Comparison between CMOS logic and micro-relays -- Bibliography -- Index -- Other titles from iSTE in Electronics Engineering -- EULA.

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