Zhang, Hanqiao.

High Speed Digital Design : Design of High Speed Interconnects and Signaling. - 1st ed. - 1 online resource (268 pages)

Front Cover -- High Speed Digital Design -- Copyright Page -- Contents -- About the Authors/Contributors -- 1 Transmission line fundamentals -- Basic Electromagnetics -- Electromagnetics Field Theory -- Maxwell's equations -- Ampere's law -- Faraday's law -- Gauss's law -- Gauss's law for magnetism -- Propagation of Plane Waves -- Uniform plane wave -- Uniform plane wave in conductive media -- Power flow and the Poynting vector -- Transmission Line Theory -- Wave Equations on Lossless Transmission Lines -- Lossless transmission line -- Wave propagation on a lossless transmission line -- Incident waves and reflected waves -- Impedance, Reflection Coefficient, and Power Flow on a Lossless Transmission Line -- Input impedance and reflection coefficient -- Power flow on a lossless transmission line -- Traveling and Standing Waves on a Transmission Line -- Traveling waves -- Standing waves -- Transmission Line Structures -- Stripline -- Microstrip -- Coplanar Waveguides -- Novel Transmission Lines -- References -- 2 PCB design for signal integrity -- Differential Signaling -- Impedance -- Time Domain Analysis -- Eye Diagram -- Jitter -- Jitter components and budget -- Jitter amplification example -- Frequency Domain Analysis -- Spectral Content -- Insertion Loss -- Integrated Insertion Loss Noise -- Return Loss -- S11 nulls -- Crosstalk -- Crosstalk sum -- Integrated Crosstalk -- Signal-to-Noise Ratio -- Stack-Up Design -- Impedance Target (Routing Impedance) -- Optimal routing impedance -- PCB Losses -- Dielectric Loss -- Lower loss dielectrics -- Hybrid stackups -- Conductor Loss -- Surface roughness -- Crosstalk Mitigation through StackUp -- Stripline dielectric -- Solder mask -- Dual Stripline -- PCB stackup -- Angled routing -- Parallelism -- Densely Broadside Coupled Dual Stripline -- Via Stub Mitigation -- Impedance optimization -- U-turn via. Back-drilling -- Blind and buried via -- PCB Layout Optimization -- Length Matching -- Fiber Weave Effect -- Crosstalk Reduction -- Interleaving -- Guard trace -- Signal-to-ground ratio -- Ground placement -- Orthogonal placement -- Component (vertical to horizontal) cancellation -- Non-Ideal Return Path -- Power Integrity -- Repeaters -- Introduction to re-timers -- Introduction to re-drivers -- Modeling and simulation -- PCIe considerations -- References -- 3 Channel modeling and simulation -- Transmission Lines -- Causality -- Checking for Model Causality -- Causal Frequency-Dependent Model -- Copper Surface Roughness -- Modified Hammerstad model -- Huray model -- Conductivity -- Environmental Impact -- Humidity -- Conductivity -- Temperature -- Model and simulation -- Model Geometries -- Stripline structures -- Microstrip structures -- Corner Models -- Iterative corner model -- Monte Carlo corner model -- Ideal Assumptions: Homogeneous Impedance -- Ideal Assumptions: Crosstalk Aggressors -- Transmitters -- IBIS Models -- Spice Voltage Source Model -- Linearity test -- 3D Modeling -- Ports/Terminals -- Wave ports -- Lumped ports -- Model Analysis Settings -- Discrete or interpolating solutions -- Frequency range and step size -- Port order -- Normalize result to 50ohms -- Plated-Through-Hole Via -- Model Techniques -- Pre-Layout Approximation -- Pre-Layout Modeling -- Post-Layout -- Connectors -- Connector Variability -- Signal Selection -- Separated Via Models -- Unconnected Pins -- Physical Features -- Design Optimization -- Voiding edge fingers -- Voiding SMT connector pads -- Packages -- C4 Escape -- Transmission Line -- PTH Via -- BGA Model -- Signal Selection for 3D Package Structures -- References -- 4 Link circuits and architecture -- Types of Link Circuit Architectures -- Embedded Clock Architecture -- Forwarded Clock Architecture. Termination -- DC and AC Coupling -- Termination Type -- Termination Circuits -- Termination Calibration Circuits -- Termination Detection Circuits -- Transmitter -- Transmitter Equalization -- Transmitter Data Path -- Current-Mode Driver -- Voltage-Mode Driver -- Receiver -- Receiver Equalization -- Receiver Data Path -- Continuous-Time Linear Equalizer -- Decision Feedback Equalizer -- Data Sampler -- Error Sampler -- Receiver Calibration -- Receiver Adaptation -- Clock and Data Recovery -- Clock and Data Recovery Loop -- Phase Detectors -- Forwarded Clock Receiver -- Delay-Locked Loop -- Design for Test/Manufacture -- Analog DFx Features -- Digital DFx Features -- References -- 5 Measurement and data acquisition techniques -- Digital Oscilloscope Measurement -- Real-Time and Equivalent-Time Sampling Scopes -- Bandwidth -- Scope Digital Filter Applications -- TDR Measurements -- De-skew Differential Pairs with TDR -- Channel Characterization with TDR -- Return Loss Measurement with TDR -- Vector Network Analyzer Measurement -- What is VNA? -- VNA Error Sources and Calibration -- Full Two-Port SOLT Calibration Procedure -- Example of Measurement Using VNA -- VNA Measurement Procedure -- References -- 6 Designing and validating with Intel processors -- Designing Systems with Intel Devices -- Interconnect Model -- Equalization Models -- Transmit feed forward equalization -- Continuous time linear equalizer -- Decision feedback equalizer -- Equalized pulse response -- Automatic Equalization Adaptation -- Performance Analysis -- Spice bit by bit -- Empirical convolution -- Peak distortion analysis -- Statistical analysis -- Solution from design of experiments -- Solution from Typical Models -- System Validation with Intel Devices -- Power-on Preparations -- Types of I/O Design Validation -- System Margining Validation Overview. DDR System Margining Validation -- High-Speed Serial I/O Margining Validation -- Low-Margin Debug Guidance -- Summary -- References -- Index.

ISBN: 9780124186675

Subjects--Topical Terms:
Digital electronics.

Index Terms--Genre/Form:
Electronic books.

LC Class. No.: TK7868.D5.Z43 2015

Dewey Class. No.: 621.3/98