TY - BOOK AU - Yang,Won Y. AU - Kim,Jaekwon AU - Park,Kyung W. AU - Baek,Donghyun AU - Lim,Sungjoon AU - Joung,Jingon AU - Park,Suhyun AU - Lee,Han L. AU - Choi,Woo June AU - Im,Taeho TI - Electronic Circuits with MATLAB, PSpice, and Smith Chart SN - 9781119598978 AV - TK7867 .Y364 2020 PY - 2020/// CY - Newark PB - John Wiley & Sons, Incorporated KW - Electronic circuit design-Data processing KW - Electronic books N1 - Cover -- Title Page -- Copyright Page -- Contents -- Preface -- About the Companion Website -- Chapter 1 Load Line Analysis and Fourier Series -- 1.1 Load Line Analysis -- 1.1.1 Load Line Analysis of a Nonlinear Resistor Circuit -- 1.1.2 Load Line Analysis of a Nonlinear RL circuit -- 1.2 Voltage-Current Source Transformation -- 1.3 Thevenin/Norton Equivalent Circuits -- 1.4 Miller's Theorem -- 1.5 Fourier Series -- 1.5.1 Computation of Fourier Coefficients Using Symmetry -- 1.5.2 Circuit Analysis Using Fourier Series -- 1.5.3 RMS Value and Distortion Factor of a Non-Sinusoidal Periodic Signal -- Problems -- Chapter 2 Diode Circuits -- 2.1 The v-i Characteristic of Diodes -- 2.1.1 Large-Signal Diode Model for Switching Operations -- 2.1.2 Small-Signal Diode Model for Amplifying Operations -- 2.2 Analysis/Simulation of Diode Circuits -- 2.2.1 Examples of Diode Circuits -- 2.2.2 Clipper/Clamper Circuits -- 2.2.3 Half-wave Rectifier -- 2.2.4 Half-wave Rectifier with Capacitor - Peak Rectifier -- 2.2.5 Full-wave Rectifier -- 2.2.6 Full-wave Rectifier with LC Filter -- 2.2.7 Precision Rectifiers -- 2.2.7.1 Improved Precision Half-wave Rectifier -- 2.2.7.2 Precision Full-wave Rectifier -- 2.2.8 Small-Signal (AC) Analysis of Diode Circuits -- 2.3 Zender Diodes -- Problems -- Chapter 3 BJT Circuits -- 3.1 BJT (Bipolar Junction Transistor) -- 3.1.1 Ebers-Moll Representation of BJT -- 3.1.2 Operation Modes (Regions) of BJT -- 3.1.3 Parameters of BJT -- 3.1.4 Common-Base Configuration -- 3.1.5 Common-Emitter Configuration -- 3.1.6 Large-Signal (DC) Model of BJT -- 3.1.7 Small-Signal (AC) Model of BJT -- 3.1.8 Analysis of BJT Circuits -- 3.1.9 BJT Current Mirror -- 3.1.10 BJT Inverter/Switch -- 3.1.11 Emitter-Coupled Differential Pair -- 3.2 BJT Amplifier Circuits -- 3.2.1 Common-Emitter (CE) Amplifier; 3.2.2 Common-Collector (CC) Amplifier (Emitter Follower) -- 3.2.3 Common-Base (CB) Amplifier -- 3.2.4 Multistage Cascaded BJT Amplifier -- 3.2.5 Composite/Compound Multi-Stage BJT Amplifier -- 3.3 Logic Gates Using Diodes/Transistors[C-3, M-1] -- 3.3.1 DTL NAND Gate -- 3.3.2 TTL NAND Gate -- 3.3.2.1 Basic TTL NAND Gate Using Two BJTs -- 3.3.2.2 TTL NAND Gate Using Three BJTs -- 3.3.2.3 Totem-Pole Output Stage -- 3.3.2.4 Open-Collector Output and Tristate Output -- 3.3.3 ECL (Emitter-Coupled Logic) OR/NOR Gate -- 3.4 Design of BJT Amplifier -- 3.4.1 Design of CE Amplifier with Specified Voltage Gain -- 3.4.2 Design of CC Amplifier (Emitter Follower) with Specified Input Resistance -- 3.5 BJT Amplifier Frequency Response -- 3.5.1 CE Amplifier -- 3.5.2 CC Amplifier (Emitter Follower) -- 3.5.3 CB Amplifier -- 3.6 BJT Inverter Time Response -- Problems -- Chapter 4 FET Circuits -- 4.1 Field-Effect Transistor (FET) -- 4.1.1 JFET (Junction FET) -- 4.1.2 MOSFET (Metal-Oxide-Semiconductor FET) -- 4.1.3 MOSFET Used as a Resistor -- 4.1.4 FET Current Mirror -- 4.1.5 MOSFET Inverter -- 4.1.5.1 NMOS Inverter Using an Enhancement NMOS as a Load -- 4.1.5.2 NMOS Inverter Using a Depletion NMOS as a Load -- 4.1.5.3 CMOS Inverter -- 4.1.6 Source-Coupled Differential Pair -- 4.1.7 CMOS Logic Circuits -- 4.2 FET Amplifer -- 4.2.1 Common-Source (CS) Amplifier -- 4.2.2 CD Amplifier (Source Follower) -- 4.2.3 Common-Gate (CG) Amplifier -- 4.2.4 Common-Source (CS) Amplifier with FET Load -- 4.2.4.1 CS Amplifier with an Enhancement FET Load -- 4.2.4.2 CS Amplifier with a Depletion FET Load -- 4.2.5 Multistage FET Amplifiers -- 4.3 Design of FET Amplifier -- 4.3.1 Design of CS Amplifier -- 4.3.2 Design of CD Amplifier -- 4.4 FET Amplifier Frequency Response -- 4.4.1 CS Amplifier -- 4.4.2 CD Amplifier (Source Follower) -- 4.4.3 CG Amplifier -- 4.5 FET Inverter Time Response; Problems -- Chapter 5 OP Amp Circuits -- 5.1 OP Amp Basics [Y-1] -- 5.2 OP Amp Circuits with Resistors [Y-1] -- 5.2.1 OP Amp Circuits with Negative Feedback -- 5.2.1.1 Inverting OP Amp Circuit -- 5.2.1.2 Non-Inverting OP Amp Circuit -- 5.2.1.3 Voltage Follower -- 5.2.1.4 Linear Combiner -- 5.2.2 OP Amp Circuits with Positive Feedback -- 5.2.2.1 Inverting Positive Feedback OP Amp Circuit -- 5.2.2.2 Non-Inverting Positive Feedback OP Amp Circuit -- 5.3 First-Order OP Amp Circuits [Y-1] -- 5.3.1 First-Order OP Amp Circuits with Negative Feedback -- 5.3.2 First-Order OP Amp Circuits with Positive Feedback -- 5.3.2.1 Square(Rectangular)-Wave Generator -- 5.3.2.2 Rectangular/Triangular-Wave Generator -- 5.3.3 555 Timer Using OP Amp as Comparator -- 5.4 Second-Order OP Amp Circuits [Y-1] -- 5.4.1 MFB (Multi-FeedBack) Topology -- 5.4.2 Sallen-Key Topology -- 5.5 Active Filter [Y-1] -- 5.5.1 First-Order Active Filter -- 5.5.2 Second-Order Active LPF/HPF -- 5.5.3 Second-Order Active BPF -- 5.5.4 Second-Order Active BSF -- Problems -- Chapter 6 Analog Filter -- 6.1 Analog Filter Design -- 6.2 Passive Filter -- 6.2.1 Low-pass Filter (LPF) -- 6.2.1.1 Series LR Circuit -- 6.2.1.2 Series RC Circuit -- 6.2.2 High-pass Filter (HPF) -- 6.2.2.1 Series CR Circuit -- 6.2.2.2 Series RL Circuit -- 6.2.3 Band-pass Filter (BPF) -- 6.2.3.1 Series Resistor, an Inductor, and a Capacitor (RLC) Circuit and Series Resonance -- 6.2.3.2 Parallel RLC Circuit and Parallel Resonance -- 6.2.4 Band-stop Filter (BSF) -- 6.2.4.1 Series RLC Circuit -- 6.2.4.2 Parallel RLC Circuit -- 6.2.5 Quality Factor -- 6.2.6 Insertion Loss -- 6.2.7 Frequency Scaling and Transformation -- 6.3 Passive Filter Realization -- 6.3.1 LC Ladder -- 6.3.2 L-Type Impedance Matcher -- 6.3.3 T- and -Type Impedance Matchers -- 6.3.4 Tapped-C Impedance Matchers -- 6.4 Active Filter Realization -- Problems; Chapter 7 Smith Chart and Impedance Matching -- 7.1 Transmission Line -- 7.2 Smith Chart -- 7.3 Impedance Matching Using Smith Chart -- 7.3.1 Reactance Effect of a Lossless Line -- 7.3.2 Single-Stub Impedance Matching -- 7.3.2.1 Shunt-Connected Single Stub -- 7.3.2.2 Series-Connected Single Stub -- 7.3.3 Double-Stub Impedance Matching -- 7.3.4 The Quarter-Wave Transformer -- 7.3.4.1 Binomial Multisection QWT -- 7.3.4.2 Chebyshev Multisection QWT -- 7.3.5 Filter Implementation Using Stubs[P-1] -- 7.3.6 Impedance Matching with Lumped Elements -- Problems -- Chapter 8 Two-Port Network and Parameters -- 8.1 Two-Port Parameters [Y-1] -- 8.1.1 Definitions and Examples of Two-Port Parameters -- 8.1.2 Relationships Among Two-Port Parameters -- 8.1.3 Interconnection of Two-Port Networks -- 8.1.3.1 Series Connection and z-parameters -- 8.1.3.2 Parallel (Shunt) Connection and y-parameters -- 8.1.3.3 Series-Parallel(Shunt) Connection and h-parameters -- 8.1.3.4 Parallel(Shunt)-Series Connection and g-parameters -- 8.1.3.5 Cascade Connection and a-parameters -- 8.1.4 Curse of Port Condition -- 8.1.5 Circuit Models with Given Parameters -- 8.1.5.1 Circuit Model with Given z-parameters -- 8.1.5.2 Circuit Model with Given y-parameters -- 8.1.5.3 Circuit Model with Given a/b-parameters -- 8.1.5.4 Circuit Model with Given h/g-parameters -- 8.1.6 Properties of Two-Port Networks with Source/Load -- 8.2 Scattering Parameters -- 8.2.1 Definition of Scattering Parameters -- 8.2.2 Two-Port Network with Source/Load -- 8.3 Gain and Stability -- 8.3.1 Two-Port Power Gains [L-1, P-1] -- 8.3.2 Stability [E-1, L-1, P-1] -- 8.3.3 Design for Maximum Gain [M-2, P-1] -- 8.3.4 Design for Specified Gain [M-2, P-1] -- Problems -- Appendix A Laplace Transform -- Definition of Laplace Transform -- Inverse Laplace Transform -- Laplace Transform of Electric Circuits; Appendix B Matrix Operations with MATLAB -- B.1 Addition and Subtraction -- B.2 Multiplication -- B.3 Determinant -- B.4 Inverse Matrix -- B.5 Solution of a Set of Linear Equations Using Inverse Matrix -- B.6 Operations on Matrices and Vectors Using MATLAB -- Appendix C Complex Number Operations with MATLAB -- C.1 Addition -- C.2 Multiplication -- C.3 Division -- C.4 Conversion between Rectangular Form and Polar/Exponential Form -- C.5 Operations on Complex Numbers Using MATLAB -- Appendix D Nonlinear/Differential Equations with MATLAB -- D.1 Nonlinear Equation Solver -- D.2 Differential Equation Solver -- Appendix E Symbolic Computations with MATLAB -- E.1 How to Declare Symbolic Variables and Handle Symbolic Expressions -- E.2 Solving Algebraic Equations -- Appendix F Useful Formulas -- Appendix G Standard Values of Resistors, Capacitors, and Inductors -- G.1 Color Code of Resistors -- G.2 Standard Values of Resistors -- G.3 Standard Values of Capacitors -- G.4 Standard Values of Inductors -- G.5 Standard Values of Zener Diode Voltage -- Appendix H OrCAD/PSpice® -- H.1 Starting Capture Component Information System (CIS) Session -- H.2 Drawing Schematic -- H.2.1 Fetching Parts (Place> -- Part or `p´) -- H.2.2 Placing Parts -- H.2.3 Defining(Assigning)/Changing Part Values -- H.2.4 Wiring (Place> -- Wire or `w´) -- H.3 Setting Simulation Conditions -- H.3.1 Creating Simulation Profile -- H.3.2 Placing Voltage/Current Markers (Probes) - PSpice> -- Markers -- H.3.3 Editing Simulation Profile -- H.4 Running PSpice Simulation and Observing the Results -- H.4.1 Analyzing Waveforms - Trace> -- Cursor -- H.4.2 Adding/Removing Waveforms - Trace> -- Add_Trace or `Ins´/Del key -- H.4.3 Processing Waveforms/Graph -- H.4.4 Initial Transient Bias Point -- H.4.5 Viewing Output File and Netlist File -- H.5 Circuit Analysis Using OrCAD/Capture; H.5.1 DC Sweep Analysis UR - https://ebookcentral.proquest.com/lib/orpp/detail.action?docID=5988979 ER -