Digital Circuit Analysis and Design with Simulink Modeling.

Digital Circuit Analysis &amp -- Design Front Cover 2nd Edition.pdf -- Digital Circuits SECOND Edition Front Matter.pdf -- Digital Circuits SECOND Edition Preface.pdf -- Digital Circuits SECOND Edition TOC All Chapters.pdf -- Digital Circuits SECOND Edition Chapter 01.pdf -- Chapter 1 -- 1.1 Decimal, Binary, Octal, and Hexadecimal Systems -- 1.2 Binary, Octal, and Hexadecimal to Decimal Conversions -- 1.3 Decimal to Binary, Octal, and Hexadecimal Conversions -- 1.4 Binary-Octal-Hexadecimal Conversions -- 1.5 Summary -- 1.6 Exercises -- 1.7 Solutions to End-of-Chapter Exercises -- Digital Circuits SECOND Edition Chapter 02.pdf -- Chapter 2 -- Operations in Binary, Octal, and Hexadecimal Systems -- 2.1 Binary System Operations -- 2.2 Octal System Operations -- 2.3 Hexadecimal System Operations -- 2.4 Complements of Numbers -- 2.4.1 Tens-Complement -- 2.4.2 Nines-Complement -- 2.4.3 Twos-Complement -- 2.4.4 Ones-Complement -- 2.5 Subtraction with Tens- and Twos-Complements -- 2.6 Subtraction with Nines- and Ones-Complements -- 2.7 Summary -- 2.8 Exercises -- 2.9 Solutions to End-of-Chapter Exercises -- Digital Circuits SECOND Edition Chapter 03.pdf -- Chapter 3 -- 3.1 Signed Magnitude of Binary Numbers -- 3.2 Floating Point Arithmetic -- 3.2.1 The IEEE Single Precision Floating Point Arithmetic -- 3.2.2 The IEEE Double Precision Floating Point Arithmetic -- 3.3 Summary -- 3.4 Exercises -- 3.5 Solutions to End-of-Chapter Exercises -- Digital Circuits SECOND Edition Chapter 04.pdf -- Chapter 4 -- 4.1 Encoding -- 4.1.1 Binary Coded Decimal (BCD) -- 4.1.2 The Excess-3 Code -- 4.1.3 The 2*421 Code -- 4.1.4 The Gray Code -- 4.2 The American Standard Code for Information Interchange (ASCII) Code -- 4.3 The Extended Binary Coded Decimal Interchange Code (EBCDIC) -- 4.4 Parity Bits -- 4.5 Error Detecting and Correcting Codes -- 4.6 Cyclic Codes.

4.7 Summary -- 4.8 Exercises -- 4.9 Solutions to End-of-Chapter Exercises -- Digital Circuits SECOND Edition Chapter 05.pdf -- Chapter 5 -- 5.1 Basic Logic Operations -- 5.2 Fundamentals of Boolean Algebra -- 5.2.1 Postulates -- 5.2.2 Theorems -- 5.3 Truth Tables -- 5.4 Summary -- 5.5 Exercises -- 5.6 Solutions to End-of-Chapter Exercises -- Digital Circuits SECOND Edition Chapter 06.pdf -- Chapter 6 -- 6.1 Minterms -- 6.2 Maxterms -- 6.3 Conversion from One Standard Form to Another -- 6.4 Properties of Minterms and Maxterms -- 6.5 Summary -- 6.6 Exercises -- 6.7 Solutions to End-of-Chapter Exercises -- Digital Circuits SECOND Edition Chapter 07.pdf -- Chapter 7 -- 7.1 Implementation of Logic Diagrams from Boolean Expressions -- 7.2 Obtaining Boolean Expressions from Logic Diagrams -- 7.3 Input and Output Waveforms -- 7.4 Karnaugh Maps -- 7.4.1 K-map of Two Variables -- 7.4.2 K-map of Three Variables -- 7.4.3 K-map of Four Variables -- 7.4.4 General Procedures for Using a K-map of n Squares -- 7.4.5 Don't Care Conditions -- 7.5 Design of Common Logic Circuits -- 7.5.1 Parity Generators/Checkers -- 7.5.2 Digital Encoders -- 7.5.3 Decimal-to-BCD Encoder -- 7.5.4 Digital Decoders -- 7.5.5 Equality Comparators -- 7.5.6 Multiplexers and Demultiplexers -- 7.5.7 Arithmetic Adder and Subtractor Logic Circuits -- 7.6 Summary -- 7.7 Exercises -- 7.8 Solutions to End-of-Chapter Exercises -- Digital Circuits SECOND Edition Chapter 08.pdf -- Chapter 8 -- 8.1 Introduction to Sequential Circuits -- 8.2 Set-Reset (SR) Flip Flop -- 8.3 Data (D) Flip Flop -- 8.4 JK Flip Flop -- 8.5 Toggle (T) Flip Flop -- 8.6 Flip Flop Triggering -- 8.7 Edge-Triggered Flip Flops -- 8.8 Master / Slave Flip Flops -- 8.9 Conversion from One Type of Flip Flop to Another -- 8.10 Analysis of Synchronous Sequential Circuits -- 8.11 Design of Synchronous Counters -- 8.12 Registers.

8.13 Ring Counters -- 8.14 Ring Oscillators -- 8.15 Summary -- 8.16 Exercises -- 8.17 Solutions to End-of-Chapter Exercises -- Digital Circuits SECOND Edition Chapter 09.pdf -- Chapter 9 -- 9.1 Random-Access Memory (RAM) -- 9.2 Read-Only Memory (ROM) -- 9.3 Programmable Read-Only Memory (PROM) -- 9.4 Erasable Programmable Read-Only Memory (EPROM) -- 9.5 Electrically-Erasable Programmable Read-Only Memory (EEPROM) -- 9.6 Flash Memory -- 9.7 Memory Sticks -- 9.8 Cache Memory -- 9.9 Virtual Memory -- 9.10 Scratch Pad Memory -- 9.11 The Simulink Memory Block -- 9.12 Summary -- 9.13 Exercises -- 9.14 Solutions to End-of-Chapter Exercises -- Digital Circuits SECOND Edition Chapter 10.pdf -- Chapter 10 -- 10.1 Computers Defined -- 10.2 Basic Digital Computer System Organization and Operation -- 10.3 Parallel Adder -- 10.4 Serial Adder -- 10.5 Overflow Conditions -- 10.6 High-Speed Addition and Subtraction -- 10.7 Binary Multiplication -- 10.8 Binary Division -- 10.9 Logic Operations of the ALU -- 10.10 Other ALU functions -- 10.11 Logic and Bit Operations with Simulink Blocks -- 10.11.1 The Logical Operator Block -- 10.11.2 The Relational Operator Block -- 10.11.3 The Interval Test Block -- 10.11.4 The Interval Test Dynamic Block -- 10.11.5 The Combinatorial Logic Block -- 10.11.6 The Compare to Zero Block -- 10.11.7 The Compare to Constant Block -- 10.11.8 The Bit Set Block -- 10.11.9 The Clear Bit Block -- 10.11.10 The Bitwise Operator Block -- 10.11.11 The Shift Arithmetic Block -- 10.11.12 The Extract Bits Block -- 10.12 Summary -- 10.13 Exercises -- 10.14 Solutions to End-of-Chapter Exercises -- Digital Circuits SECOND Edition Chapter 11.pdf -- Chapter 11 -- 11.1 Programmable Logic Arrays (PLAs) -- 11.2 Programmable Array Logic (PAL) -- 11.3 Complex Programmable Logic Devices (CPLDs) -- 11.3.1 The Altera MAX 7000 Family of CPLDs.

11.3.2 The AMD Mach Family of CPLDs -- 11.3.3 The Lattice Family of CPLDs -- 11.3.4 Cypress Flash370 Family of CPLDs -- 11.3.5 Xilinx XC9500 Family of CPLDs -- 11.3.6 CPLD Applications -- 11.4 Field Programmable Gate Arrays (FPGAs) -- 11.4.1 SRAM-Based FPGA Architecture -- 11.4.2 Xilinx FPGAs -- 11.4.3 Atmel FPGAs -- 11.4.4 Altera FPGAs -- 11.4.5 Lattice FPGAs -- 11.4.6 Antifuse-Based FPGAs -- 11.4.7 Actel FPGAs -- 11.4.8 QuickLogic FPGAs -- 11.5 FPGA Block Configuration - Xilinx FPGA Resources -- 11.6 The CPLD versus FPGA Trade-Off -- 11.7 What is Next -- 11.8 Summary -- 11.9 Exercises -- 11.10 Solutions to End-of-Chapter Exercises -- Digital Circuits SECOND Edition Appendix A.pdf -- Appendix A -- A.1 Command Window -- A.2 Roots of Polynomials -- A.3 Polynomial Construction from Known Roots -- A.4 Evaluation of a Polynomial at Specified Values -- A.5 Rational Polynomials -- A.6 Using MATLAB to Make Plots -- A.7 Subplots -- A.8 Multiplication, Division and Exponentiation -- A.9 Script and Function Files -- A.10 Display Formats -- Digital Circuits SECOND Edition Appendix B.pdf -- Appendix B -- B.1 Simulink and its Relation to MATLAB -- B.2 Simulink Demos -- Digital Circuits SECOND Edition Appendix C.pdf -- Appendix C -- C.1 Introduction -- C.2 Basic Structure of an ABEL Source File -- C.3 Declarations -- C.4 Numbers -- C.5 Directives -- C.5.1 The @alternate Directive -- C.5.2 The @radix Directive -- C.5.3 The @standard Directive -- C.6 Sets -- C.6.1 Indexing or Accessing a Set -- A.6.2 Set Operations -- C.7 Operators -- C.7.1 Logical Operators -- C.7.2 Arithmetic Operators -- C.7.3 Relational Operators -- C.7.4 Assignment Operators -- C.7.5 Operator Priorities -- C.8 Logic Description -- C.8.1 Equations -- C.8.2 Truth Tables -- C.8.3 State Diagram -- C.8.4 Dot Extensions -- C.9 Test Vectors -- C.10 Property Statements -- C.11 Active-Low Declarations.

Digital Circuits SECOND Edition Appendix D.pdf -- Appendix D -- D.1 Introduction -- D.2 The VHDL Design Approach -- D.3 VHDL as a Programming Language -- D.3.1 Elements -- D.3.2 Comments -- D.3.3 Identifiers -- D.3.4 Literal Numbers -- D.3.5 Literal Characters -- D.3.6 Literal Strings -- D.3.7 Bit Strings -- D.3.8 Data Types -- D.3.9 Integer Types -- D.3.10 Physical Types -- D.3.11 Floating Point Types -- D.3.12 Enumeration Types -- D.3.13 Arrays -- D.3.14 Records -- D.3.15 Subtypes -- D.3.16 Object Declarations -- D.3.17 Attributes -- D.3.18 Expressions and Operators -- D.3.19 Sequential Statements -- D.3.20 Variable Assignments -- D.3.21 If Statement -- D.3.22 Case Statement -- D.3.23 Loop Statements -- D.3.24 Null Statement -- D.3.25 Assertions -- D.3.26 Subprograms and Packages -- D.3.27 Procedures and Functions -- D.3.28 Overloading -- D.3.29 Package and Package Body Declarations -- D.3.30 Package Use and Name Visibility -- D.4 Structural Description -- D.4.1 Entity Declarations -- D.4.2 Architecture Declarations -- D.4.3 Signal Declarations -- D.4.4 Blocks -- D.4.5 Component Declarations -- D.4.6 Component Instantiation -- D.5 Behavioral Description -- D.5.1 Signal Assignment -- D.5.2 Process and the Wait Statement -- D.5.3 Concurrent Signal Assignment Statements -- D.5.4 Conditional Signal Assignment -- D.5.5 Selected Signal Assignment -- D.6 Organization -- D.6.1 Design Units and Libraries -- D.6.2 Configurations -- D.7 Design Example -- Digital Circuits SECOND Edition Appendix E.pdf -- Appendix E -- E.1 Description -- E.2 Verilog Applications -- E.3 The Verilog Programming Language -- E.4 Lexical Conventions -- E.5 Program Structure -- E.6 Data Types -- E.6.1 Physical Data Types -- E.6.2 Abstract Data Types -- E.7 Operators -- E.7.1 Binary Arithmetic Operators -- E.7.2 Unary Arithmetic Operators -- E.7.3 Relational Operators.

E.7.4 Logical Operators.

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Electronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2024. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries.