Digital Integrated Circuits : Analysis and Design, Second Edition.

Cover -- Half Title -- Title Page -- Copyright Page -- Dedication -- Table of Contents -- About the Author -- Preface -- 1: Introduction -- 1.1 Historical Perspective and Moore's Law -- 1.2 Electrical Properties of Digital Integrated Circuits -- 1.2.1 Logic Function -- 1.2.2 Static Voltage Transfer Characteristics -- 1.2.3 Transient Characteristics -- 1.2.4 Fan-In and Fan-Out -- 1.2.5 Dissipation -- 1.2.6 Power Delay Product -- 1.3 Computer-Aided Design and Verifi cation -- 1.4 Fabrication -- 1.5 Semiconductors and Junctions -- 1.6 The MOS Transistor -- 1.7 MOS Gate Circuits -- 1.8 Interconnect -- 1.9 Dynamic CMOS -- 1.10 Low-Power CMOS -- 1.11 Bistable Circuits -- 1.12 Memories -- 1.13 Input/Output and Interface Circuits -- 1.14 Practical Perspective -- 1.15 Summary -- 1.16 Exercises -- References -- 2: Fabrication -- 2.1 Introduction -- 2.2 Basic CMOS Fabrication Sequence -- 2.3 Advanced Processing for High-Performance CMOS -- 2.3.1 Copper Metal -- 2.3.2 Metal Gates -- 2.3.3 High-k Gate Dielectric -- 2.4 Lithography and Masks -- 2.5 Layout and Design Rules -- 2.5.1 Minimum Line Widths and Spacings -- 2.5.2 Contacts and Vias -- 2.6 Testing and Yield -- 2.7 Packaging -- 2.8 Burn-In and Accelerated Testing -- 2.9 Practical Perspective -- 2.10 Summary -- 2.11 Exercises -- References -- 3: Semiconductors and p-n Junctions -- 3.1 Introduction -- 3.2 Crystal Structure of Silicon -- 3.3 Energy Bands -- 3.4 Carrier Concentrations -- 3.4.1 Intrinsic Silicon -- 3.4.2 n-Type Silicon -- 3.4.3 p-Type Silicon -- 3.5 Current Transport -- 3.6 Carrier Continuity Equations -- 3.7 Poisson's Equation -- 3.8 The p-n Junction -- 3.8.1 Zero Bias (Thermal Equilibrium) -- 3.8.1.1 Built-In Voltage Vbi -- 3.8.1.2 Depletion Width W -- 3.8.2 Depletion Capacitance -- 3.8.3 Forward Bias Current -- 3.8.3.1 Short-Base n+-p Junction -- 3.8.3.2 Long-Base n+-p Junction.

3.8.4 Reverse Bias -- 3.8.5 Reverse Breakdown -- 3.9 Metal-Semiconductor Junctions -- 3.10 SPICE Models -- 3.11 Practical Perspective -- 3.12 Summary -- 3.13 Exercises -- References -- 4: The MOS Transistor -- 4.1 Introduction -- 4.2 The MOS Capacitor -- 4.3 Threshold Voltage -- 4.4 MOSFET Current-Voltage Characteristics -- 4.4.1 Linear Operation -- 4.4.2 Saturation Operation -- 4.4.3 Subthreshold Operation -- 4.4.4 Transit Time -- 4.5 Short-Channel MOSFETs -- 4.5.1 The Short-Channel Effect -- 4.5.2 Narrow-Channel Effect -- 4.5.3 Drain-Induced Barrier Lowering -- 4.5.4 Channel Length Modulation -- 4.5.5 Field-Dependent Mobility and Velocity Saturation -- 4.5.6 Transit Time in Short-Channel MOSFETs -- 4.6 MOSFET Design -- 4.7 MOSFET Capacitances -- 4.7.1 Oxide Capacitances -- 4.7.2 p-n Junction Capacitances -- 4.7.3 The Miller Effect -- 4.8 MOSFET Constant-Field Scaling -- 4.9 SPICE MOSFET Models -- 4.9.1 MOSFET Level 1 Model -- 4.9.2 Berkeley Short-Channel Insulated Gate Field Effect Transistor Model -- 4.9.2.1 BSIM1 Parameters -- 4.9.2.2 BSIM1 Threshold Voltage -- 4.9.2.3 BSIM1 Drain Current-Linear Region -- 4.9.2.4 BSIM1 Drain Current-Saturation Region -- 4.9.2.5 BSIM1 Drain Current-Subthreshold Region -- 4.9.2.6 Hand Calculations Related to the BSIM1 -- 4.10 SPICE Demonstrations -- 4.11 Practical Perspective -- 4.12 Summary -- 4.13 Exercises -- References -- 5: MOS Gate Circuits -- 5.1 Inverter Static Characteristics -- 5.2 Critical Voltages -- 5.2.1 Output High-Voltage VOH -- 5.2.2 Output Low-Voltage VOL -- 5.2.3 Input Low-Voltage VIL -- 5.2.4 Input High-Voltage VIH -- 5.2.5 Switching Threshold (Midpoint) Voltage VM -- 5.2 Dissipation -- 5.4 Propagation Delays -- 5.5 Fan-Out -- 5.6 NOR Circuits -- 5.7 NAND Circuits -- 5.8 Exclusive OR (XOR) Circuit -- 5.9 General Logic Design -- 5.10 Pass Transistor Circuits -- 5.11 SPICE Demonstrations.

5.12 Practical Perspective -- 5.13 Summary -- 5.14 Exercises -- 6: Static CMOS -- 6.1 Introduction -- 6.2 Voltage Transfer Characteristic -- 6.2.1 Voltage Regime One: n-MOS Cutoff and p-MOS Linear -- 6.2.2 Voltage Regime Two: n-MOS Saturated and p-MOS Linear -- 6.2.3 Voltage Regime Three: Both MOSFETs Saturated -- 6.2.4 Voltage Regime Four: n-MOS Linear and p-MOS Saturated -- 6.2.5 Voltage Regime Five: n-MOS Linear and p-MOS Cutoff -- 6.3 Load Surface Analysis -- 6.4 Critical Voltages -- 6.4.1 Input Low-Voltage V IL -- 6.4.2 Switching Threshold VM -- 6.4.3 Input High-Voltage VIH -- 6.5 Crossover (Short-Circuit) Current -- 6.5.1 Current Regime One: n-MOS Cutoff -- 6.5.2 Current Regime Two: n-MOS Saturated -- 6.5.3 Current Regime Three: p-MOS Saturated -- 6.5.4 Current Regime Four: p-MOS Cutoff -- 6.5.5 Unifi ed Expression for the Crossover Current -- 6.5.6 Effect of Threshold Voltages -- 6.6 Propagation Delays -- 6.6.1 High-to-Low Propagation Delay tPHL -- 6.6.2 Low-to-High Propagation Delay tPLH -- 6.6.3 Propagation Delay Design Equations -- 6.6.4 Propagation Delays in the Symmetric Inverter -- 6.6.5 Approximate Expressions for the Propagation Delays -- 6.6.6 Effect of the Input Rise and Fall Time -- 6.7 Inverter Rise and Fall Times -- 6.7.1 Fall Time -- 6.7.2 Rise Time -- 6.7.3 Effect of the Input Rise and Fall Time on Output Rise and Fall Time -- 6.8 Propagation Delays in Short-Channel CMOS -- 6.8.1 High-to-Low Propagation Delay tPHL in Short-Channel CMOS -- 6.8.2 Low-to-High Propagation Delay tPLH in Short-Channel CMOS -- 6.8.3 Comparison of the Short-Channel and Long-Channel Delay Equations -- 6.8.4 Propagation Delay Design Equations for Short-Channel CMOS -- 6.9 Power Dissipation -- 6.9.1 Capacitance Switching Dissipation -- 6.9.2 Short-Circuit Dissipation -- 6.9.3 Leakage Current Dissipation -- 6.10 Fan-Out.

6.11 Circuit Delays as Functions of Fan-Out -- 6.12 CMOS Ring Oscillator -- 6.13 CMOS Inverter Design -- 6.14 CMOS NAND Circuits -- 6.14.1 Sizing of Transistors in a CMOS NAND Gate -- 6.14.2 Static Characteristics of the CMOS NAND Gate -- 6.14.3 Dynamic Characteristics of the CMOS NAND Gate -- 6.15 CMOS NOR Circuits -- 6.16 Other Logic Functions in CMOS -- 6.16.1 Transistor Sizing in CMOS AND-OR-INVERT Gates -- 6.17 74HC Series CMOS -- 6.18 Pseudo NMOS Circuits -- 6.19 Scaling of CMOS -- 6.19.1 Full Scaling of CMOS -- 6.19.2 Constant Voltage Scaling of CMOS -- 6.20 Latch-Up in CMOS -- 6.21 SPICE Demonstrations -- 6.22 Summary -- 6.23 Practical Perspective -- 6.24 Exercises -- 7: Interconnect -- 7.1 Introduction -- 7.2 Capacitance of Interconnect -- 7.3 Resistance of Interconnect -- 7.4 Inductance of Interconnect -- 7.5 Modeling Interconnect Delays -- 7.5.1 Lumped Capacitance Model -- 7.5.2 Distributed Models -- 7.5.3 Transmission Line Model -- 7.6 Crosstalk -- 7.7 Polysilicon Interconnect -- 7.8 SPICE Demonstrations -- 7.9 Practical Perspective -- 7.10 Summary -- 7.11 Exercises -- References -- 8: Dynamic CMOS -- 8.1 Introduction -- 8.2 Rise Time -- 8.3 Fall Time -- 8.4 Charge Sharing -- 8.5 Charge Retention -- 8.6 Logic Design -- 8.7 Alternative Form Using a p-MOS Pull-Up Network -- 8.8 Cascading of Dynamic Logic Circuits -- 8.9 Domino Logic -- 8.10 Multiple-Output Domino Logic -- 8.11 Zipper Logic -- 8.12 Dynamic Pass Transistor Circuits -- 8.12.1 Logic "1" Transfer Delay t1 -- 8.12.2 Logic "0" Transfer Delay t0 -- 8.13 CMOS Transmission Gate Circuits -- 8.14 SPICE Demonstrations -- 8.15 Practical Perspective -- 8.16 Summary -- 8.17 Exercises -- References -- 9: Low-Power CMOS -- 9.1 Introduction -- 9.2 Low-Voltage CMOS -- 9.3 Multiple Voltage CMOS -- 9.4 Dynamic Voltage Scaling -- 9.5 Active Body Biasing -- 9.6 Multiple-Threshold CMOS.

9.7 Adiabatic Logic -- 9.8 Silicon-on-Insulator -- 9.8.1 SOI Technologies: SIMOX and Wafer Bonding -- 9.8.2 SOI MOSFETs: Fully Depleted or Partially Depleted -- 9.8.3 SOI for Low-Power CMOS -- 9.9 Practical Perspective -- 9.10 Summary -- 9.11 Exercises -- References -- 10: Bistable Circuits -- 10.1 Introduction -- 10.2 Set-Reset Latch -- 10.3 SR Flip-Flop -- 10.4 JK Flip-Flops -- 10.5 Other Flip-Flops -- 10.6 Schmitt Triggers -- 10.6.1 CMOS Schmitt Trigger -- 10.7 SPICE Demonstrations -- 10.8 Practical Perspective -- 10.9 Summary -- 10.10 Exercises -- References -- 11: Digital Memories -- 11.1 Introduction -- 11.2 Static Random Access Memory -- 11.2.1 CMOS SRAM Cell -- 11.2.2 NMOS SRAM Cell -- 11.2.3 SRAM Sense Amplifiers -- 11.3 Dynamic Random Access Memory -- 11.4 Read-Only Memory -- 11.4.1 NOR Read-Only Memory -- 11.4.2 NAND Read-Only Memory -- 11.5 Programmable Read-Only Memory -- 11.6 Erasable Programmable Read-Only Memory -- 11.7 Electrically Erasable Programmable Read-Only Memory -- 11.8 Flash Memory -- 11.9 Other Nonvolatile Memories -- 11.10 Access Times in Digital Memories -- 11.11 Row and Column Decoder Design -- 11.12 Practical Perspective -- 11.13 Summary -- 11.14 Exercises -- References -- 12: Input/Output and Interface Circuits -- 12.1 Introduction -- 12.2 Input Electrostatic Discharge Protection -- 12.3 Input Enable Circuits -- 12.3.1 CMOS Transmission Gate -- 12.3.1.1 Regime One: n-MOS Linear and p-MOS Cutoff -- 12.3.1.2 Regime Two: n-MOS Linear and p-MOS Linear -- 12.3.1.3 Regime Three: n-MOS Cutoff and p-MOS Linear -- 12.3.1.4 Overall Characteristic of CMOS Transmission Gate -- 12.4 CMOS Output Buffers -- 12.5 Tri-State Outputs -- 12.6 Interface Circuits -- 12.6.1 High-Voltage CMOS to Low-Voltage CMOS -- 12.6.2 Low-Voltage CMOS to High-Voltage CMOS -- 12.7 SPICE Demonstrations -- 12.8 Summary -- 12.9 Practical Perspective.

12.10 Exercises.

Digital Integrated Circuits, Second Edition, has been completely rewritten to emphasize submicron device physics and the importance of dynamic and low-power logic circuits. Providing a revised instructional text for engineers involved with Very Large Scale Integrated Circuit design and fabrication, this second edition delves into the dramatic advances, including new applications and changes in the physics of operation made possible by relentless miniaturization. Each chapter includes numerous worked examples, case studies and SPICE computer simulations. The book's website offers supplementary material and more worked problems.

Description based on publisher supplied metadata and other sources.

Electronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2024. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries.