Digital Electronics 3 : Finite-State Machines.

Cover -- Title Page -- Copyright -- Contents -- Preface -- Summary -- The reader -- 1. Synchronous Finite State Machines -- 1.1. Introduction -- 1.2. State diagram -- 1.3. Design of synchronous finite state machines -- 1.4. Examples -- 1.4.1. Flip-flops -- 1.4.2. Binary sequence detector -- 1.4.2.1. Mealy model -- 1.4.2.2. Moore model -- 1.4.3. State machine implementation based on a state table -- 1.4.3.1. D flip-flop -- 1.4.3.2. JK flip-flop -- 1.4.4. Variable width pulse generator -- 1.5. Equivalent states and minimization of the number of states -- 1.5.1. Implication table method -- 1.5.1.1. Example 1 -- 1.5.1.2. Example 2 -- 1.5.1.3. Example 3 -- 1.5.2. Partitioning method -- 1.5.2.1. Example 1 -- 1.5.2.2. Example 2 -- 1.5.2.3. Example 3 -- 1.5.3. Simplification of incompletely specified machines -- 1.5.3.1. Definition and basic concepts -- 1.5.3.2. Example 1 -- 1.5.3.3. Example 2 -- 1.5.3.4. Example 3 -- 1.6. State encoding -- 1.7. Transformation of Moore and Mealy state machines -- 1.8. Splitting finite state machines -- 1.8.1. Rules for splitting -- 1.8.2. Example 1 -- 1.8.3. Example 2 -- 1.9. Sequence detector implementation based on a programmable circuit -- 1.10. Practical considerations -- 1.10.1. Propagation delays and race conditions -- 1.10.2. Timing specifications -- 1.11. Exercises -- 1.12. Solutions -- 2. Algorithmic State Machines -- 2.1. Introduction -- 2.2. Structure of an ASM -- 2.3. ASM chart -- 2.4. Applications -- 2.4.1. Serial adder/subtracter -- 2.4.2. Multiplier based on addition and shift operations -- 2.4.3. Divider based on subtraction and shift operations -- 2.4.4. Controller for an automatic vending machine -- 2.4.5. Traffic light controller -- 2.5. Exercises -- 2.6. Solutions -- 3. Asynchronous Finite State Machines -- 3.1. Introduction -- 3.2. Overview -- 3.3. Gated D latch -- 3.4. Muller C-element.

3.5. Self-timed circuit -- 3.6. Encoding the states of an asynchronous state machine -- 3.7. Synthesis of asynchronous circuits -- 3.7.1. Oscillatory cycle -- 3.7.2. Essential and d-trio hazards -- 3.7.2.1. Essential hazard -- 3.7.2.2. d-trio hazard -- 3.7.2.3. Essential and d-trio hazard detection -- 3.7.3. Design of asynchronous state machines -- 3.8. Application examples of asynchronous state machines -- 3.8.1. Pulse synchronizer -- 3.8.2. Asynchronous counter -- 3.9. Implementation of asynchronous machines using SR latches or C-elements -- 3.10. Asynchronous state machine operating in pulse mode -- 3.11. Asynchronous state machine operating in burst mode -- 3.12. Exercises -- 3.13. Solutions -- Appendix. Overview of VHDL Language -- A.1. Introduction -- A.2. Principles of VHDL -- A.2.1. Names -- A.2.2. Comments -- A.2.3. Library and packages -- A.2.4. Ports -- A.2.5. Signal and variable -- A.2.6. Data types and objects -- A.2.7. Attributes -- A.2.8. Entity and architecture -- A.3. Concurrent instructions -- A.3.1. Concurrent instructions with selective assignment -- A.3.2. Concurrent instructions with conditional assignment -- A.4. Components -- A.4.1. Generics -- A.4.2. The GENERATE Instruction -- A.4.3. Process -- A.5. Sequential structures -- A.5.1. The IF instruction -- A.5.2. CASE instruction -- A.6. Testbench -- Bibliography -- Index -- Other titles from iSTE in Electronics Engineering -- EULA.

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