High Speed Digital Design : (Record no. 55160)
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| 000 -LEADER | |
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| fixed length control field | 07517nam a22004933i 4500 |
| 001 - CONTROL NUMBER | |
| control field | EBC2166539 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | MiAaPQ |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20240729123844.0 |
| 006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS | |
| fixed length control field | m o d | |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION | |
| fixed length control field | cr cnu|||||||| |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 240724s2015 xx o ||||0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9780124186675 |
| Qualifying information | (electronic bk.) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| Canceled/invalid ISBN | 9780124186637 |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (MiAaPQ)EBC2166539 |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (Au-PeEL)EBL2166539 |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (CaPaEBR)ebr11090975 |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (CaONFJC)MIL823217 |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (OCoLC)922847744 |
| 040 ## - CATALOGING SOURCE | |
| Original cataloging agency | MiAaPQ |
| Language of cataloging | eng |
| Description conventions | rda |
| -- | pn |
| Transcribing agency | MiAaPQ |
| Modifying agency | MiAaPQ |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER | |
| Classification number | TK7868.D5.Z43 2015 |
| 082 0# - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.3/98 |
| 100 1# - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Zhang, Hanqiao. |
| 245 10 - TITLE STATEMENT | |
| Title | High Speed Digital Design : |
| Remainder of title | Design of High Speed Interconnects and Signaling. |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 1st ed. |
| 264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE | |
| Place of production, publication, distribution, manufacture | San Diego : |
| Name of producer, publisher, distributor, manufacturer | Elsevier Science & Technology, |
| Date of production, publication, distribution, manufacture, or copyright notice | 2015. |
| 264 #4 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE | |
| Date of production, publication, distribution, manufacture, or copyright notice | ©2015. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 1 online resource (268 pages) |
| 336 ## - CONTENT TYPE | |
| Content type term | text |
| Content type code | txt |
| Source | rdacontent |
| 337 ## - MEDIA TYPE | |
| Media type term | computer |
| Media type code | c |
| Source | rdamedia |
| 338 ## - CARRIER TYPE | |
| Carrier type term | online resource |
| Carrier type code | cr |
| Source | rdacarrier |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Front Cover -- High Speed Digital Design -- Copyright Page -- Contents -- About the Authors/Contributors -- 1 Transmission line fundamentals -- Basic Electromagnetics -- Electromagnetics Field Theory -- Maxwell's equations -- Ampere's law -- Faraday's law -- Gauss's law -- Gauss's law for magnetism -- Propagation of Plane Waves -- Uniform plane wave -- Uniform plane wave in conductive media -- Power flow and the Poynting vector -- Transmission Line Theory -- Wave Equations on Lossless Transmission Lines -- Lossless transmission line -- Wave propagation on a lossless transmission line -- Incident waves and reflected waves -- Impedance, Reflection Coefficient, and Power Flow on a Lossless Transmission Line -- Input impedance and reflection coefficient -- Power flow on a lossless transmission line -- Traveling and Standing Waves on a Transmission Line -- Traveling waves -- Standing waves -- Transmission Line Structures -- Stripline -- Microstrip -- Coplanar Waveguides -- Novel Transmission Lines -- References -- 2 PCB design for signal integrity -- Differential Signaling -- Impedance -- Time Domain Analysis -- Eye Diagram -- Jitter -- Jitter components and budget -- Jitter amplification example -- Frequency Domain Analysis -- Spectral Content -- Insertion Loss -- Integrated Insertion Loss Noise -- Return Loss -- S11 nulls -- Crosstalk -- Crosstalk sum -- Integrated Crosstalk -- Signal-to-Noise Ratio -- Stack-Up Design -- Impedance Target (Routing Impedance) -- Optimal routing impedance -- PCB Losses -- Dielectric Loss -- Lower loss dielectrics -- Hybrid stackups -- Conductor Loss -- Surface roughness -- Crosstalk Mitigation through StackUp -- Stripline dielectric -- Solder mask -- Dual Stripline -- PCB stackup -- Angled routing -- Parallelism -- Densely Broadside Coupled Dual Stripline -- Via Stub Mitigation -- Impedance optimization -- U-turn via. |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Back-drilling -- Blind and buried via -- PCB Layout Optimization -- Length Matching -- Fiber Weave Effect -- Crosstalk Reduction -- Interleaving -- Guard trace -- Signal-to-ground ratio -- Ground placement -- Orthogonal placement -- Component (vertical to horizontal) cancellation -- Non-Ideal Return Path -- Power Integrity -- Repeaters -- Introduction to re-timers -- Introduction to re-drivers -- Modeling and simulation -- PCIe considerations -- References -- 3 Channel modeling and simulation -- Transmission Lines -- Causality -- Checking for Model Causality -- Causal Frequency-Dependent Model -- Copper Surface Roughness -- Modified Hammerstad model -- Huray model -- Conductivity -- Environmental Impact -- Humidity -- Conductivity -- Temperature -- Model and simulation -- Model Geometries -- Stripline structures -- Microstrip structures -- Corner Models -- Iterative corner model -- Monte Carlo corner model -- Ideal Assumptions: Homogeneous Impedance -- Ideal Assumptions: Crosstalk Aggressors -- Transmitters -- IBIS Models -- Spice Voltage Source Model -- Linearity test -- 3D Modeling -- Ports/Terminals -- Wave ports -- Lumped ports -- Model Analysis Settings -- Discrete or interpolating solutions -- Frequency range and step size -- Port order -- Normalize result to 50ohms -- Plated-Through-Hole Via -- Model Techniques -- Pre-Layout Approximation -- Pre-Layout Modeling -- Post-Layout -- Connectors -- Connector Variability -- Signal Selection -- Separated Via Models -- Unconnected Pins -- Physical Features -- Design Optimization -- Voiding edge fingers -- Voiding SMT connector pads -- Packages -- C4 Escape -- Transmission Line -- PTH Via -- BGA Model -- Signal Selection for 3D Package Structures -- References -- 4 Link circuits and architecture -- Types of Link Circuit Architectures -- Embedded Clock Architecture -- Forwarded Clock Architecture. |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Termination -- DC and AC Coupling -- Termination Type -- Termination Circuits -- Termination Calibration Circuits -- Termination Detection Circuits -- Transmitter -- Transmitter Equalization -- Transmitter Data Path -- Current-Mode Driver -- Voltage-Mode Driver -- Receiver -- Receiver Equalization -- Receiver Data Path -- Continuous-Time Linear Equalizer -- Decision Feedback Equalizer -- Data Sampler -- Error Sampler -- Receiver Calibration -- Receiver Adaptation -- Clock and Data Recovery -- Clock and Data Recovery Loop -- Phase Detectors -- Forwarded Clock Receiver -- Delay-Locked Loop -- Design for Test/Manufacture -- Analog DFx Features -- Digital DFx Features -- References -- 5 Measurement and data acquisition techniques -- Digital Oscilloscope Measurement -- Real-Time and Equivalent-Time Sampling Scopes -- Bandwidth -- Scope Digital Filter Applications -- TDR Measurements -- De-skew Differential Pairs with TDR -- Channel Characterization with TDR -- Return Loss Measurement with TDR -- Vector Network Analyzer Measurement -- What is VNA? -- VNA Error Sources and Calibration -- Full Two-Port SOLT Calibration Procedure -- Example of Measurement Using VNA -- VNA Measurement Procedure -- References -- 6 Designing and validating with Intel processors -- Designing Systems with Intel Devices -- Interconnect Model -- Equalization Models -- Transmit feed forward equalization -- Continuous time linear equalizer -- Decision feedback equalizer -- Equalized pulse response -- Automatic Equalization Adaptation -- Performance Analysis -- Spice bit by bit -- Empirical convolution -- Peak distortion analysis -- Statistical analysis -- Solution from design of experiments -- Solution from Typical Models -- System Validation with Intel Devices -- Power-on Preparations -- Types of I/O Design Validation -- System Margining Validation Overview. |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | DDR System Margining Validation -- High-Speed Serial I/O Margining Validation -- Low-Margin Debug Guidance -- Summary -- References -- Index. |
| 588 ## - SOURCE OF DESCRIPTION NOTE | |
| Source of description note | Description based on publisher supplied metadata and other sources. |
| 590 ## - LOCAL NOTE (RLIN) | |
| Local note | Electronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2024. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Digital electronics. |
| 655 #4 - INDEX TERM--GENRE/FORM | |
| Genre/form data or focus term | Electronic books. |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Krooswyk, Steven. |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Ou, Jeffrey. |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Relationship information | Print version: |
| Main entry heading | Zhang, Hanqiao |
| Title | High Speed Digital Design |
| Place, publisher, and date of publication | San Diego : Elsevier Science & Technology,c2015 |
| International Standard Book Number | 9780124186637 |
| 797 2# - LOCAL ADDED ENTRY--CORPORATE NAME (RLIN) | |
| Corporate name or jurisdiction name as entry element | ProQuest (Firm) |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | <a href="https://ebookcentral.proquest.com/lib/orpp/detail.action?docID=2166539">https://ebookcentral.proquest.com/lib/orpp/detail.action?docID=2166539</a> |
| Public note | Click to View |
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