Architecture-Aware Optimization Strategies in Real-Time Image Processing. (Record no. 132171)
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| 000 -LEADER | |
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| fixed length control field | 05071nam a22004573i 4500 |
| 001 - CONTROL NUMBER | |
| control field | EBC5122088 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | MiAaPQ |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20240729131547.0 |
| 006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS | |
| fixed length control field | m o d | |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION | |
| fixed length control field | cr cnu|||||||| |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 240724s2017 xx o ||||0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9781119467144 |
| Qualifying information | (electronic bk.) |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| Canceled/invalid ISBN | 9781786300942 |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (MiAaPQ)EBC5122088 |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (Au-PeEL)EBL5122088 |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (CaPaEBR)ebr11463977 |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (OCoLC)1008962948 |
| 040 ## - CATALOGING SOURCE | |
| Original cataloging agency | MiAaPQ |
| Language of cataloging | eng |
| Description conventions | rda |
| -- | pn |
| Transcribing agency | MiAaPQ |
| Modifying agency | MiAaPQ |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER | |
| Classification number | TA1637.C436 2017 |
| 082 0# - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.367 |
| 100 1# - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Li, Chao. |
| 245 10 - TITLE STATEMENT | |
| Title | Architecture-Aware Optimization Strategies in Real-Time Image Processing. |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 1st ed. |
| 264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE | |
| Place of production, publication, distribution, manufacture | Newark : |
| Name of producer, publisher, distributor, manufacturer | John Wiley & Sons, Incorporated, |
| Date of production, publication, distribution, manufacture, or copyright notice | 2017. |
| 264 #4 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE | |
| Date of production, publication, distribution, manufacture, or copyright notice | ©2017. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 1 online resource (185 pages) |
| 336 ## - CONTENT TYPE | |
| Content type term | text |
| Content type code | txt |
| Source | rdacontent |
| 337 ## - MEDIA TYPE | |
| Media type term | computer |
| Media type code | c |
| Source | rdamedia |
| 338 ## - CARRIER TYPE | |
| Carrier type term | online resource |
| Carrier type code | cr |
| Source | rdacarrier |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Cover -- Half-Title Page -- Title Page -- Copyright Page -- Contents -- Preface -- 1. Introduction of Real-time Image Processing -- 1.1. General image processing presentation -- 1.2. Real-time image processing -- 2. Hardware Architectures for Real-time Processing -- 2.1. History of image processing hardware platforms -- 2.2. General-purpose processors -- 2.3. Digital signal processors -- 2.4. Graphics processing units -- 2.5. Field programmable gate arrays -- 2.6. SW/HW codesign of real-time image processing -- 2.7. Image processing development environment description -- 2.8. Comparison and discussion -- 3. Rapid Prototyping of Parallel Reconfigurable Instruction Set Processor for Efficient Real-Time Image Processing -- 3.1. Context and problematic -- 3.2. Related works -- 3.3. Design exploration framework -- 3.4. Case study: RISP conception and synthesis for spatial transforms -- 3.4.1. Digital DCT algorithm implementations -- 3.4.2. Rapid prototyping of DCT RISP conception -- 3.4.3. RISP simulation and synthesis for 2D-DCT -- 3.5. Hardware implementation of spatial transforms on an FPGA-based platform -- 3.6. Discussion and conclusion -- 4. Exploration of High-level Synthesis Technique -- 4.1. Introduction of HLS technique -- 4.2. Vivado_HLS process presentation -- 4.2.1. Control and datapath extraction -- 4.2.2. Scheduling and binding -- 4.3. Case of HLS application: FPGA implementation of an improved skin lesion assessment method -- 4.3.1. KMGA method description -- 4.3.2. KMGA method optimization -- 4.3.3. HCR-KMGA implementation onto FPGA using HLS technique -- 4.3.4. Implementation evaluation experiments -- 4.4. Discussion -- 5. CDMS4HLS: A Novel Source-To-Source Compilation Strategy for HLS-Based FPGA Design -- 5.1. S2S compiler-based HLS design framework -- 5.2. CDMS4HLS compilation process description -- 5.2.1. Function inline. |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | 5.2.2. Loop manipulation -- 5.2.3. Symbolic expression manipulation -- 5.2.4. Loop unwinding -- 5.2.5. Memory manipulation -- 5.3. CDMS4HLS compilation process evaluation -- 5.3.1. Performances improvement evaluation -- 5.3.2. Comparison experiment -- 5.4. Discussion -- 6. Embedded Implementation of VHR Satellite Image Segmentation -- 6.1. LSM description -- 6.1.1. Background -- 6.1.2. Level set equation -- 6.1.3. LBM solver -- 6.2. Implementation and optimization presentation -- 6.2.1. Design flow description -- 6.2.2. Algorithm analysis -- 6.2.3. Function inline -- 6.2.4. Loop manipulation -- 6.2.5. Symbol expression manipulation -- 6.2.6. Loop unwinding -- 6.3. Experiment evaluation -- 6.3.1. Parameter configuration -- 6.3.2. Function verification -- 6.3.3. Optimization evaluation -- 6.3.4. Performance comparison -- 6.4. Discussion and conclusion -- 7. Real-time Image Processing with Very High-level Synthesis -- 7.1. VHLS motivation -- 7.2. Image processing from Matlab to FPGA-RTL -- 7.3. VHLS process presentation -- 7.3.1. Dynamic variable -- 7.3.2. Operation polymorphism problem -- 7.3.3. Built-in function problem -- 7.4. VHLS implementation issues -- 7.4.1. Work flow -- 7.4.2. Intermediate code versus RTL -- 7.4.3. SSC versus HLS -- 7.4.4. Verification and evaluation -- 7.5. Future work for real-time image processing with VHLS -- Bibliography -- Index -- Other titles from iSTE in Digital Signal and Image Processing -- EULA. |
| 588 ## - SOURCE OF DESCRIPTION NOTE | |
| Source of description note | Description based on publisher supplied metadata and other sources. |
| 590 ## - LOCAL NOTE (RLIN) | |
| Local note | Electronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2024. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Image processing--Digital techniques. |
| 655 #4 - INDEX TERM--GENRE/FORM | |
| Genre/form data or focus term | Electronic books. |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Balla-Arabe, Souleymane. |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Yang, Fan. |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Relationship information | Print version: |
| Main entry heading | Li, Chao |
| Title | Architecture-Aware Optimization Strategies in Real-Time Image Processing |
| Place, publisher, and date of publication | Newark : John Wiley & Sons, Incorporated,c2017 |
| International Standard Book Number | 9781786300942 |
| 797 2# - LOCAL ADDED ENTRY--CORPORATE NAME (RLIN) | |
| Corporate name or jurisdiction name as entry element | ProQuest (Firm) |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | <a href="https://ebookcentral.proquest.com/lib/orpp/detail.action?docID=5122088">https://ebookcentral.proquest.com/lib/orpp/detail.action?docID=5122088</a> |
| Public note | Click to View |
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