Nanomagnetic and Spintronic Devices for Energy-Efficient Memory and Computing. (Record no. 105175)
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| fixed length control field | 09425nam a22004693i 4500 |
| 001 - CONTROL NUMBER | |
| control field | EBC4385974 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | MiAaPQ |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20240729130233.0 |
| 006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS | |
| fixed length control field | m o d | |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION | |
| fixed length control field | cr cnu|||||||| |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 240724s2016 xx o ||||0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9781118869253 |
| Qualifying information | (electronic bk.) |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (MiAaPQ)EBC4385974 |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (Au-PeEL)EBL4385974 |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (CaPaEBR)ebr11152624 |
| 035 ## - SYSTEM CONTROL NUMBER | |
| System control number | (OCoLC)922799345 |
| 040 ## - CATALOGING SOURCE | |
| Original cataloging agency | MiAaPQ |
| Language of cataloging | eng |
| Description conventions | rda |
| -- | pn |
| Transcribing agency | MiAaPQ |
| Modifying agency | MiAaPQ |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER | |
| Classification number | TK7895.M3 -- .N366 2016eb |
| 082 0# - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.3973 |
| 100 1# - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Atulasimha, Jayasimha. |
| 245 10 - TITLE STATEMENT | |
| Title | Nanomagnetic and Spintronic Devices for Energy-Efficient Memory and Computing. |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 1st ed. |
| 264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE | |
| Place of production, publication, distribution, manufacture | Newark : |
| Name of producer, publisher, distributor, manufacturer | John Wiley & Sons, Incorporated, |
| Date of production, publication, distribution, manufacture, or copyright notice | 2016. |
| 264 #4 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE | |
| Date of production, publication, distribution, manufacture, or copyright notice | ©2015. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 1 online resource (359 pages) |
| 336 ## - CONTENT TYPE | |
| Content type term | text |
| Content type code | txt |
| Source | rdacontent |
| 337 ## - MEDIA TYPE | |
| Media type term | computer |
| Media type code | c |
| Source | rdamedia |
| 338 ## - CARRIER TYPE | |
| Carrier type term | online resource |
| Carrier type code | cr |
| Source | rdacarrier |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Intro -- Nanomagnetic and Spintronic Devices for Energy-Efficient Memory and Computing -- Contents -- About the Editors and Acknowledgments -- Jayasimha Atulasimha -- Supriyo Bandyopadhyay -- Acknowledgments -- List of Contributors -- Foreword -- Preface -- 1 Introduction to Spintronic and Nanomagnetic Computing Devices -- 1.1 Spintronic Devices -- 1.2 Nanomagnetic Devices -- 1.2.1 Use of Spin Torque to Switch Nanomagnets -- 1.2.2 Other Methodologies for Switching Nanomagnets -- 1.3 Thinking beyond Traditional Boolean Logic -- References -- 2 Potential Applications of all Electric Spin Valves Made of Asymmetrically Biased Quantum Point Contacts -- 2.1 Introduction -- 2.2 Quantum Point Contacts -- 2.3 Spin Orbit Coupling -- 2.3.1 Rashba SOC (RSOC) -- 2.3.2 Dresselhaus SOC (DSOC) -- 2.3.3 Lateral Spin-Orbit Coupling (LSOC) -- 2.4 Importance of Spin Relaxation in 1D Channels -- 2.5 Observation of a 0.5 Conductance Plateau in Asymmetrically Biased QPCs in the Presence of LSOC -- 2.5.1 Early Experimental Results Using InAs QPCs -- 2.5.2 NEGF Conductance Calculations -- 2.5.3 Spin Texture Associated with Conductance Anomalies in QPCs -- 2.5.4 Prospect for Generation of Spin Polarized Current at Higher Temperature -- 2.5.5 Observation of Other Anomalous Conductance Plateaus in an Asymmetrically Biased InAs/In0.52 Al0.48 as QPCs -- 2.6 Intrinsic Bistability near Conductance Anomalies -- 2.6.1 Experimental Results -- 2.6.2 NEGF Simulations -- 2.7 QPC Structures with Four In-plane SGs: Toward an All Electrical Spin Valve -- 2.7.1 Preliminary Results on Four-gate QPCs -- 2.7.2 Experiments -- 2.7.3 Onset of Hysteresis and Negative Resistance Region -- 2.8 Future Work -- 2.9 Summary -- Acknowledgments -- References -- 3 Spin-Transistor Technology for Spintronics/CMOS Hybrid Logic Circuits and Systems -- 3.1 Spin-Transistor and Pseudo-Spin-Transistor. |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | 3.1.1 Spin - MOSFET -- 3.1.2 Pseudo-Spin-MOSFET -- 3.2 Energy-Efficient Logic Applications of Spin-Transistors -- 3.2.1 Power Gating with Nonvolatile Retention -- 3.2.2 Nonvolatile Bistable Circuits -- 3.2.3 Break-even Time -- 3.3 Nonvolatile SRAM Technology -- 3.3.1 Static Noise Margin of Nonvolatile SRAM -- 3.3.2 Energy Performance of NV-SRAM -- 3.4 Application of Nonvolatile Bistable Circuits for Memory Systems -- References -- 4 Spin Transfer Torque: A Multiscale Picture -- 4.1 Introduction -- 4.1.1 Background -- 4.1.2 STT Modeling: An Integrated Approach -- 4.2 The Physics of Spin Transfer Torque -- 4.2.1 Free-Electron Model for Magnetic Tunnel Junction -- 4.3 First Principles Evaluation of TMR and STT -- 4.3.1 The TMR Effect in the MgO Barrier -- 4.3.2 Currents and Torques in NEGF -- 4.3.3 First Principles Results on Spin Transfer Torque -- 4.4 Magnetization Dynamics -- 4.4.1 Landau-Lifshitz-Gilbert Equation -- 4.4.2 Spin Torque Switching in Presence of Thermal Fluctuations -- 4.4.3 Including Thermal Fluctuations: Stochastic LLG vs Fokker Planck -- 4.5 Summary: Multiscaling from Atomic Structure to Error Rate -- Acknowledgments -- References -- 5 Magnetic Tunnel Junction Based Integrated Logics and Computational Circuits -- 5.1 Introduction -- 5.2 GMR Based Field Programmable Devices -- 5.3 MTJ Based Field Programmable Devices -- 5.3.1 MTJ Structure and TMR Ratio -- 5.3.2 MTJ Based Magneto-Logic -- 5.3.3 Utilization of STT in MTJ Based Magneto-Logic -- 5.4 Information Transformation between Gates -- 5.4.1 Direct Communication Using Charge Current -- 5.4.2 Magnetic Domain Walls for Information Transferring -- 5.5 MTJ Based Logic-in-Memory Devices -- 5.6 Magnetic Quantum Cellular Automata -- 5.6.1 Introduction and Background -- 5.6.2 Experimental Demonstrations -- 5.7 All-Spin Based Magnetic Logic -- 5.7.1 Nonlocal Lateral Spin Valve Background. |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | 5.7.2 Critical Parameters for Operation -- 5.7.3 Selected Review of Experimental Demonstrations -- 5.7.4 Applications to All-Spin Logic Devices -- 5.8 Summary -- Acknowledgment -- References -- 6 Magnetization Switching and Domain Wall Motion Due to Spin Orbit Torque -- 6.1 Introduction -- 6.2 Theory -- 6.2.1 Rashba Effect -- 6.2.2 Spin Hall Effect -- 6.3 Magnetic Switching Driven by Spin Orbit Torque -- 6.4 Domain Wall Motion Driven by Spin Orbit Torque -- 6.5 Applications of Spin Orbit Torque -- 6.6 Conclusion -- References -- 7 Magnonic Logic Devices -- 7.1 Introduction -- 7.2 Magnonic Logic Devices -- 7.3 Spin Wave-Based Logic Gates and Architectures -- 7.4 Discussion and Summary -- References -- 8 Strain Mediated Magnetoelectric Memory -- 8.1 Introduction -- 8.2 Concept of Unequivocal Strain- or Stress-Switched Nanomagnetic Memory -- 8.2.1 Magnetic Configuration and Equilibrium Positions -- 8.2.2 Quasi-Static Stress-Mediated Switching -- 8.3 LLG Simulations - Macrospin Model -- 8.3.1 Landau-Lifshitz-Gilbert Equation and Effective Magnetic Field -- 8.3.2 Memory Parameters -- 8.3.3 Results of the Macrospin Model -- 8.4 LLG Simulations - Eshelby Approach -- 8.4.1 Geometry of the Memory Element -- 8.4.2 Coupling with the External Magnetic Field -- 8.4.3 Coupling with the External Electric Field and Elastic Stress -- 8.4.4 Static Behavior of the System -- 8.4.5 Dynamic Behavior of the System -- 8.5 Stochastic Error Analysis -- 8.5.1 Statistical Mechanics of Magnetization in a Single-Domain Particle -- 8.5.2 Switching Process within the Magnetoelectric Memory -- 8.6 Preliminary Experimental Results -- 8.6.1 Piezoelectric Actuator with in-Plane Polarization -- 8.6.2 Ferroelectric Relaxors with out-of-Plane Polarization -- 8.6.3 Magnetoelastic Switching in a Magneto-Resistive Structure -- 8.7 Conclusions -- Acknowledgments -- References. |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | 9 Hybrid Spintronics-Strainronics -- 9.1 Introduction -- 9.1.1 Nanomagnetic Memory and Logic Devices: The Problem of Energy Dissipation in the Clocking Circuit -- 9.1.2 Switching Nanomagnets with Strain Could Drastically Reduce Energy Dissipation: Hybrid Spintronics-Straintronics Overview -- 9.1.3 Landau-Lifshitz-Gilbert (LLG) Equation -- 9.2 Nanomagnetic Memory Switched with Strain -- 9.2.1 Complete Magnetization Reversal (180° Switching): Complex out-of-Plane Dynamics -- 9.2.2 Switching the Magnetization between Two Mutually Perpendicular Stable Orientations and Extension to Stable Orientations with Angular Separation > -- 90° -- 9.2.3 Complete 180° Switching with Stress Alone -- 9.2.4 Mixed Mode Switching of Magnetization by 180°: Acoustically Assisted Spin Transfer Torque (STT) Switching for Nonvolatile Memory -- 9.3 Straintronic Clocking of Nanomagnetic Logic -- 9.3.1 Two-State Dipole Coupled Nanomagnetic Logic -- 9.3.2 Four-state Multiferroic Nanomagnetic Logic (NML) -- 9.3.3 Switching Error in Dipole Coupled Nanomagnetic Logic (NML) -- 9.3.4 Straintronic Nanomagnetic Logic Devices (NML) -- 9.4 Summary and Conclusions -- References -- 10 Unconventional Nanocomputing with Physical Wave Interference Functions* -- 10.1 Overview -- 10.2 Spin Waves Physical Layer for WIF Implementation -- 10.2.1 Physical Fabric Components -- 10.3 Elementary WIF Operators for Logic -- 10.4 Binary WIF Logic Design -- 10.4.1 Binary WIF Full Adder -- 10.4.2 Parallel Counters -- 10.4.3 Benchmarking Binary WIF Circuits vs. CMOS -- 10.4.4 WIF Topology Exploration -- 10.5 Multivalued WIF Logic Design -- 10.5.1 Multivalued Operators and Implementation Using WIF -- 10.5.2 Multivalued Arithmetic Circuit Example: Quaternary Full Adder -- 10.5.3 Benchmarking of WIF Multivalued Circuits vs. Conventional CMOS. |
| 505 8# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | 10.5.4 Input/Output Logic for Data Conversion between Binary and Radix-r Domains -- 10.6 Microprocessors with WIF: Opportunities and Challenges -- 10.7 Summary and Future Work -- References -- Index -- Supplemental Images -- EULA. |
| 588 ## - SOURCE OF DESCRIPTION NOTE | |
| Source of description note | Description based on publisher supplied metadata and other sources. |
| 590 ## - LOCAL NOTE (RLIN) | |
| Local note | Electronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2024. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Magnetic memory (Computers). |
| 655 #4 - INDEX TERM--GENRE/FORM | |
| Genre/form data or focus term | Electronic books. |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Bandyopadhyay, Supriyo. |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Relationship information | Print version: |
| Main entry heading | Atulasimha, Jayasimha |
| Title | Nanomagnetic and Spintronic Devices for Energy-Efficient Memory and Computing |
| Place, publisher, and date of publication | Newark : John Wiley & Sons, Incorporated,c2016 |
| 797 2# - LOCAL ADDED ENTRY--CORPORATE NAME (RLIN) | |
| Corporate name or jurisdiction name as entry element | ProQuest (Firm) |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | <a href="https://ebookcentral.proquest.com/lib/orpp/detail.action?docID=4385974">https://ebookcentral.proquest.com/lib/orpp/detail.action?docID=4385974</a> |
| Public note | Click to View |
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