High-Efficiency Load Modulation Power Amplifiers for Wireless Communications.

Intro -- High-Efficiency Load Modulation Power Amplifiers for Wireless Communications -- Contents -- Preface -- Acknowledgments -- Chapter 1 Call for Efficient Power Amplification -- 1.1 Figures of Merit of a Modern Radio Power Amplifier -- 1.1.1 Output Power -- 1.1.2 Power Gain -- 1.1.3 Power Added Efficiency -- 1.1.4 Bandwidth -- 1.1.5 Linearity -- 1.2 Evolution of Communication Signals -- 1.2.1 History and Trends of Communication Signals -- 1.2.2 Effect of Signal Evolution on PAPR -- 1.2.3 Effect of High PAPR on Figures of Merit for PAs -- 1.3 Efficient Amplification with Modulation -- 1.3.1 Bias Modulation Amplifiers -- 1.3.2 Load Modulation Amplifiers -- References -- Select Bibliography -- Chapter 2 Passive Load Impedance Tuner Design -- 2.1 Specification of Passive Load Impedance Tuners -- 2.2 Selection of Tuning Elements for Passive Impedance Tuners -- 2.3 Microwave Varactors -- 2.3.1 Varactors for Dynamic Load Modulation -- 2.3.2 MEMS Varactors -- 2.3.3 BST Varactors -- 2.3.4 Silicon Varactor Diodes -- 2.3.5 GaAs Varactor Diodes -- 2.3.6 SiC Varactor Diodes -- 2.3.7 GaN Varactor Diodes -- 2.4 High-Performance Varactor Stacks -- 2.4.1 Distortion-Free Varactor Stack -- 2.4.2 Wide Tone Spacing Varactor Stack -- 2.4.3 Narrow Tone Spacing Varactor Stack -- 2.5 Passive Impedance Tuner Topologies -- 2.5.1 L-Section Impedance Tuner -- 2.5.2 Π-Section Impedance Tuner -- 2.5.3 T-Section Impedance Tuner -- 2.5.4 Multiple Tunable Element Impedance Tuner -- References -- Selected Bibliography -- Chapter 3 Dynamic Load Modulation Power Amplifiers -- 3.1 Dynamic Load Modulation Basics -- 3.2 Passive Impedance Tuner Considerations -- 3.2.1 Topology Selection for Impedance Tuner -- 3.2.2 Design Considerations of Load Impedance Tuner -- 3.3 Varactor Driver for Dynamic Load -- 3.3.1 OPAMP Driver -- 3.3.2 FET Amplifier Driver.

3.4 PA Design for Dynamic Load -- 3.4.1 Dynamic Load Class-AB Amplifier -- 3.4.2 Dynamic Load Saturated Class-B Amplifier -- 3.4.3 Dynamic Load Class-C Amplifier -- 3.4.4 Dynamic Load Class-D Amplifier -- 3.4.5 Dynamic Load Class-E Amplifier -- 3.4.6 Dynamic Class-F Amplifier -- 3.5 Digital Signal Processing for Dynamic Load -- 3.5.1 Timing Alignment for Dynamic Load -- 3.5.2 Bandwidth Reduction of Dynamic Load Control Signal -- 3.5.3 Slew-Rate Reduction of Dynamic Load Control Signal -- 3.5.4 Linearization of Dynamic Load Amplifier -- 3.6 Measurement Methods for Dynamic Load Amplifiers -- 3.6.1 Test Bed Sync for the Dynamic Load System -- 3.6.2 Continuous-Wave Versus Complex Stimulus -- 3.6.3 Complex Stimulus Measurements Setup -- 3.6.4 Complex Characterization Techniques -- References -- Selected Bibliography -- Chapter 4 Active Load Modulation Power Amplifiers -- 4.1 Balanced Versus Doherty -- 4.2 Active Load Pulling Effect -- 4.3 Active Load Amplifiers -- 4.4 Doherty Amplifier -- 4.4.1 Impedance Inverter -- 4.4.2 Amplifier Cells -- 4.4.3 Offset Lines -- 4.4.4 Input Power Splitter -- 4.4.5 Output Doherty Combining -- 4.5 Classical Doherty Limitations and Solutions -- 4.5.1 Low Breakpoint Efficiency -- 4.5.2 Inability of Peaking Amplifier -- 4.5.3 Knee Voltage Effects -- 4.5.4 Inherent Narrowband -- 4.5.5 Memory Effects -- 4.5.6 Summary of Potential Solutions -- 4.6 Chireix PAs -- 4.6.1 Differential Mode Chireix -- 4.6.2 Common-Mode Chireix Combining -- 4.6.3 Optimal Branch Amplifiers for Chireix -- 4.6.4 Chireix Power Amplifier Design Method -- References -- Selected Bibliography -- Chapter 5 Doherty Power Amplifier Designs for Efficiency Enhancement -- 5.1 Insufficient Peaking Current Issue -- 5.2  Uneven Doherty PAs -- 5.2.1  Design Method for an Uneven Doherty PA -- 5.2.2  Linearity Considerations for an Uneven Doherty PA.

5.3  Asymmetric Doherty PAs -- 5.3.1 Principle of the Asymmetric Doherty Structure -- 5.3.2 Asymmetric Amplifier-Sized Doherty Configuration -- 5.3.3 Asymmetric Output Biased Doherty Solution -- 5.3.4  Multiway Doherty PAs -- 5.4  Harmonic Termination in Doherty PAs -- 5.5 Asymmetric Doherty Design Example -- 5.5.1  Class-P Carrier Amplifier Design -- 5.5.2 Class-F−1 Peaking Amplifier Design -- 5.5.3 Output Combining Network Design -- 5.5.4 Uneven Power Divider -- 5.5.5  System Integration and Characterization -- 5.6 Multistage Doherty PAs -- 5.7 Bias Modulation Techniques -- 5.7.1 Input Bias Modulation -- 5.7.2 Output Bias Modulation -- References -- Selected Bibliography -- Chapter 6 Load Modulation PA Design for Bandwidth Extension -- 6.1 Video Bandwidth Enhancement -- 6.1.1 Video Bandwidth Enhancement Techniques -- 6.1.2 VBW Enhanced Load Modulation Amplifiers -- 6.2 Broadband Dynamic Load Amplifiers -- 6.2.1 Broadband Topology Selection -- 6.2.2 Broadband Matching Design -- 6.2.3 Design Procedures -- 6.3 Broadband Doherty Amplifiers -- 6.3.1 Optimized Output Network -- 6.3.2 Multistage Broadband Doherty Amplifier -- 6.3.3 Multisection and Tapered Output Network -- 6.3.4 Transformerless Output Network -- 6.3.5 Varactor-Based Output Network -- 6.3.6 Octave Bandwidth Doherty Amplifiers -- 6.4 Multiband Load Modulation Amplifiers -- 6.4.1 Band Switch Amplifiers -- 6.4.2 Band Switch Doherty Amplifiers -- 6.4.3 Concurrent Multiband Amplifiers -- 6.4.4 Concurrent Multiband Doherty Amplifiers -- 6.4.5 Multiband Chireix Outphasing Transmitters -- References -- Selected Bibliography -- Chapter 7 Evolved Active Load Modulation PAs -- 7.1 Inverted Doherty PAs -- 7.1.1 Two-Way Inverted Doherty Amplifiers Without Impedance Inverter -- 7.1.2 Offset Line Optimization on Inverted Doherty PAs -- 7.1.3 Three-Stage Inverted Doherty.

7.1.4 Series-Connected Load Inverted Doherty -- 7.1.5 Design Example of a Two-Way Inverted Doherty PA -- 7.2 Serial-Type Doherty PAs -- 7.3 Digital Doherty PAs -- 7.3.1 Digital Doherty Basics -- 7.3.2 Solving Power-Dependent Phase Imbalance -- 7.3.3 Mitigating Bandwidth Limitations -- 7.4 Digital Chireix Outphasing Transmitters -- 7.4.1 Digital Chireix Outphasing Basics -- 7.4.2 Digital Chireix Outphasing with a Coupled-Line Combiner -- 7.4.3 Digital Chireix Outphasing with a Broadband Combiner -- 7.5 Multilevel LINC -- 7.5.1 Multilevel LINC Basics -- 7.5.2 Envelope-Adjusting Multilevel LINC -- 7.5.3 Gain-Adjusting Multilevel LINC -- 7.6 Asymmetric Multilevel Outphasing -- 7.6.1 Asymmetric Multilevel Outphasing Basics -- 7.6.2 AMO with Discrete Dynamic Supply Modulation -- 7.6.3 AMO with Discrete Pulse-Width Modulation -- 7.6.4 Predistortion for AMO Signal Decomposition -- References -- Selected Bibliography -- About the Author -- Index.

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